Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 485
Electrical Specifications
x16 lanes can be bifurcated to support Gen 1/2 combinations of x8 and x4 links
•Intel
®
Xeon
®
processor C5500/C3500 series x4 port: 2.5 GT/s.
Each signal is 8 b/10 b encoded with an embedded clock
Signaling bit rate of 5 Gbit/sec/lane/direction; for a x4 link, bandwidth is 2 GB/sec
in each direction
Hot Insertion and Removal supported with the addition of Hot-Plug control circuitry
Boot processor provides one x4 DMI link to the PCH
Application processor in a dual processor configuration provides one x4 PCI Express
Gen 1 (2.5 GT/s) link
The PCI Express port (muxed with DMI) is only supported in a DP configuration and
is not supported on the boot processor.
The Direct Media Interface (DMI2) in the Intel
®
Xeon
®
processor C5500/C3500 series
IIO is responsible for sending and receiving packets/commands to other components in
the system, e.g. PCH. The DMI is an extension of the standard PCI Express
specification with special commands and features added to mimic the legacy Hub
Interface. DMI2, supported by Intel
®
Xeon
®
processor C5500/C3500 series, is the
second generation extension of DMI. Further details on DMI2 can be obtained from the
DMI Specification, Revision 2.0. DMI connects the processor and the PCH chip-to-chip.
The DMI is similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth
in each direction.
Only DMI x4 configuration is supported.
In DP configurations, the DMI port of the “Non-Legacy” processor may be
configured as a single PCIe port, supporting PCIe Gen1 only.
13.1.5 SMBus Interface
SMBus interface consists of two interface pins; one is a clock, and the other is serial
data. Multiple initiator and target devices may be electrically present on the same pair
of signals. Each target recognizes a start signaling semantic, and recognizes its own 7-
bit address to identify pertinent bus traffic.
The Intel
®
Xeon
®
processor C5500/C3500 series IO SMBus acts as a slave and may be
used to give a BMC out-of-band access to various IO components. The SMBus on
processor is SMBus 2.0 compliant. For more details on the SMBus protocol see the
System Management Bus Specification 2.0.
Connected globally to the processors, and to the PCH through a common shared
bus hierarchy.
Low pin count, low speed management interface.
Provides access to configuration status registers (CSRs).