Datasheet

Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
484 Order Number: 323103-001
termination resistance for each DQ and DQS/DQS# signal via the ODT control pin. The
ODT feature improves signal integrity of the memory channel by allowing the DRAM
controller to independently turn on or off the termination resistance for any or all DRAM
devices themselves instead of on the motherboard.
13.1.3 Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
Intel
®
Xeon
®
processor C5500/C3500 series contains a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics. See
the Intel
®
Xeon
®
Processor C5500/C3500 Series Thermal / Mechanical Design Guide
for processor-specific implementation details for PECI. Generic PECI specification
details are out of the scope of this document.
The PECI interface operates at a nominal voltage set by V
TTD
. The set of DC electrical
specifications shown in Table 170 is used with devices normally operating from a V
TTD
interface supply.
13.1.3.1 Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. See Figure 84 and Table 170.
13.1.4 PCI Express/DMI
The PCI Express* interface signals are driven by transceivers designed specifically for
high-speed serial communication. All PCI Express signals are fully differential and
operate in a current mode, rather than a voltage mode. These interfaces support A/C
coupling to facilitate communication across independent power supply domains and
signal at a rate well above the flight time of the interface. (The DMI interface on the
legacy processor also supports DC coupling.) The Intel
®
Xeon
®
processor C5500/
C3500 series supports the PCI Express Base Specification, Revision 2.0.
• Point-to-point, serial bi-directional interconnect
• The processor provides up to 16 PCI Express Gen 2 (5 GT/s) lanes
Figure 84. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground