Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 483
Electrical Specifications
13.0 Electrical Specifications
13.1 Processor Signaling
The Intel
®
Xeon
®
processor C5500/C3500 series includes 1366 lands that utilize
various signaling technologies. Signals are grouped by electrical characteristics and
buffer type into various signal groups. These include Intel
®
QuickPath Interconnect,
DDR3 Channel A, DDR3 Channel B, DDR3 Channel C, PCI Express, SMBus, DMI,
Platform Environmental Control Interface (PECI), Clock, Reset and Miscellaneous,
Thermal, Test Access Port (TAP), and Processor Core Power, Power Sequencing, and No
Connect/Reserved signals. See Table 159 for details.
Detailed layout, routing, and termination guidelines corresponding to these signal
groups can be found in the applicable platform design guide. See Section 1.9, “Related
Documents”.
Intel strongly recommends performing analog simulations of all interfaces.
13.1.1 Intel
®
QuickPath Interconnect
The Intel
®
Xeon
®
processor C5500/C3500 series provides one Intel
®
QuickPath
Interconnect port for high-speed serial transfer between other enabled components.
Each port consists of two uni-directional links (for transmit and receive). A differential
signaling scheme is utilized, which consists of opposite-polarity (D_P, D_N) signal pairs.
On-die termination (ODT) is included on the processor silicon and terminated to V
SS
.
Intel chipsets also provide ODT, thus eliminating the need to terminate on the system
board. Figure 83 illustrates the active ODT.
13.1.2 DDR3 Signal Groups
The memory interface utilizes DDR3 technology, which consists of numerous signal
groups for each of the three memory channels. Each group consists of multiple signals,
which may utilize various signaling technologies. See Table 159 for further details.
On-Die Termination (ODT) is a feature that allows a DRAM device to turn on/off internal
Figure 83. Active ODT for a Differential Link Example
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Signal
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