Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
48 Order Number: 323103-001
2.1.4.3 Channel Population Requirements for Memory RAS Modes
The Intel
®
Xeon
®
processor C5500/C3500 series supports four different memory RAS
modes: Independent Channel Mode, Spare Channel Mode, Mirrored Channel Mode, and
Lockstep Channel Mode. The rules on channel population and channel matching vary by
the RAS mode used. Regardless of RAS mode, requirements for populating within a
channel given in Section 2.1.4.2 must be met at all times. Support of RAS modes
requiring matching DIMM population between channels (Sparing, Mirroring, Lockstep)
require that ECC DIMMs be populated. Independent Mode only supports non-ECC
DIMMs in addition to ECC DIMMs.
For RAS modes that require matching populations, the same slot positions across
channels must hold the same DIMM type with regards to size and organization. DIMM
timings do not have to match but timings will be set to support all DIMMs populated
(i.e., DIMMs with slower timings will force faster DIMMs to the slower common timing
modes). Intel recommends checking for correct DIMM matching, if applicable to the
RAS mode, during BIOS initialization.
2.1.4.3.1 Independent Channel Mode
Channels can be populated in any order in Independent Channel Mode. All three
channels may be populated in any order and have no matching requirements. All
channels must run at the same interface frequency, but individual channels may run at
different DIMM timings (RAS latency, CAS latency, etc.).
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access
(Intel
®
FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel
®
FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
8 DDR3-800 1N Single-rank Quad-rank
9 DDR3-800 1N Dual-rank Quad-rank
10 DDR3-800 1N Quad-rank Quad-rank
Table 14. UDIMM Population Configurations Within a Channel for Two Slots per Channel
Configuration # POR Speed 1N or 2N DIMM1 DIMM0
1 DDR3-1333, 1066, & 800 1N Empty Single-rank
2 DDR3-1333, 1066, & 800 1N Empty Dual-rank
3 DDR3-1066 & 800 2N Single-rank Single-rank
4 DDR3-1066 & 800 2N Single-rank Dual-rank
5 DDR3-1066 & 800 2N Dual-rank Single-rank
6 DDR3-1066 & 8003 2N Dual-rank Dual-rank
Table 13. DIMM Population Configurations Within a Channel for Two Slots per Channel
(Sheet 2 of 2)
Configuration # POR Speed 1N or 2N DIMM1 DIMM0