Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 45
Interfaces
2.1.4 DIMM Population Requirements
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules.
2.1.4.1 General Population Requirements
All DIMMs must be DDR3 DIMMs. Registered DIMMs must be ECC only; Unbuffered
DIMMs can be ECC or non-ECC. Mixing Registered and Unbuffered DIMMs is not
allowed. It is allowed to mix ECC and non-ECC Unbuffered DIMMs. The presence of a
single non-ECC Unbuffered DIMM will result disabling of ECC functionality.
DIMMs with different timing parameters can be installed on different slots within the
same channel, but only timings that support the slowest DIMM will be applied to all. As
a consequence, faster DIMMs will be operated at timings supported by the slowest
DIMM populated. The same interface frequency (DDR3-800, DDR3-1066, or
DDR3-1333) will be applied to all DIMMs on all channels.
For DP configurations, there is no relationship or requirements between DIMMs
installed in different sockets. That is, the IMC from one socket may be populated
differently than the IMC of the alternate socket except that the DIMMs must be of the
same type, i.e. either UDIMM or RDIMM.
2.1.4.2 Populating DIMMs Within a Channel
2.1.4.2.1 DIMM Population for Three Slots per Channel
For three DIMM slots per channel configurations, the processor requires DIMMs within a
channel to be populated starting with the DIMM slot furthest from the processor in a
“fill-furthest” approach (see Figure 7).
When populating a Quad-rank DIMM with a Single- or Dual-rank DIMM in the same
channel, the Quad-rank DIMM must be populated farthest from the processor. Quad-
rank DIMMs and UDIMMs are not allowed in three slots populated configurations. Intel
recommends checking for correct DIMM placement during BIOS initialization.
Additionally, Intel strongly recommends that all designs follow the DIMM ordering,
command clock, and control signal routing documented in Figure 7. This addressing
must be maintained to be compliant with the reference BIOS code supplied by Intel. All
allowed DIMM population configurations for three slots per channel are shown in
Table 11 and Table 12.