Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 43
Interfaces
2.1.3.6.1 Limitations
Lockstepped channels must be populated identically. That is, each DIMM in one channel
must have an identical corresponding DIMM in the alternate channel; identical in
number ranks, banks, rows, and columns. DIMMs may be of different speed grades, but
the memory controller will be configured to operate all DIMMs according to the slowest
parameters present. Only channels A and B support lockstep, the third channel is
unused in lockstep mode.
In lockstep mode, the memory controller will align read data to the slowest lane on
both channels. Read data received at different times will be buffered until both
channels complete their return. If either channel needs to throttle, both are throttled. A
common configuration control bit is used to enable refresh on both channels.
2.1.3.7 Dual/Triple - Channel Modes
The IMC supports three types of dual/triple-channel, memory addressing modes; Dual/
Triple - Channel Symmetric (Interleaved), Dual/Triple-Channel Asymmetric, and Intel
®
Flex Memory mode.
2.1.3.7.1 Triple/Dual-Channel Symmetric Mode
Also known as interleaved mode, and provides maximum performance on real world
applications. Addresses are ping-ponged between the channels after each cache line
(64-byte boundary). If there are two requests, and the second request is to an address
on the opposite channel from the first, that request can be sent before data from the
first request has returned. If two consecutive cache lines are requested, both may be
retrieved simultaneously, since they are ensured to be on opposite channels. Use Dual-
Channel Symmetric mode when both Channel A and Channel B DIMM connectors are
populated in any order, with the total amount of memory in each channel being the
same. Use Triple-Channel Symmetric mode when both Channel A, Channel B, and
Channel C DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
Note: The DRAM device technology and width may vary from one channel to the other.
2.1.3.7.2 Triple/Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in Channel A and stay there until the end of the highest rank in Channel
A, and then addresses continue from the bottom of Channel B to the top, etc. Real
world applications are unlikely to make requests that alternate between addresses that
sit on opposite channels with this memory organization, so in most cases, bandwidth is
limited to a single channel.
This mode is used when Intel
®
Flex Memory Technology is disabled and both Channel
A, Channel B, and Channel C DIMM connectors are populated in any order with the total
amount of memory in each channel being different.