Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 427
Packaging and Signal Information
12.1.12 ITP Signals
12.2 Physical Layout and Signals
The full signal map is provided in Table 150, Table 151, and Table 152.
Table 153 provides an alphabetical listing of all signal locations. Table 154 provides an
alphabetical listing of all processor signals.
Table 149. ITP Signals
Signal Names
I/O
Type
Description
BPM[7:0]# I/O
Breakpoint and Performance Monitor Signals: Outputs from the processor that
indicate the status of breakpoints and programmable counters used for monitoring
processor performance.
PRDY# O
PRDY# is a processor output used by debug tools to determine processor debug
readiness.
PREQ# I PREQ# is used by debug tools to request debug operation of the processor.
TCLK I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
TDI I TDI (Test Data In) transfers serial test data into the CPU.
TDI_M I TDI_M (Test Data In) transfers serial test data into the processor.
TDO O TDO (Test Data Out) transfers serial test data out of the CPU.
TDO_M O
TDO_M (Test Data Out) transfers serial test data out of the processor.
Note: One of the TDI pin needs to be connected to one of the TDO pins on the
board.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRST# I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. .