Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 425
Packaging and Signal Information
12.1.9 Processor Core Power Signals
PSI# O
Processor Power Status Indicator: This signal is asserted when maximum possible
processor core current consumption is less than 20 A. Assertion of this signal is an
indication that the VR controller does not currently need to be able to provide ICC
above 20 A, and the VR controller can use this information to move to more
efficient operating point. This signal will de-assert at least 3.3 us before the current
consumption will exceed 20 A. The minimum PSI# assertion and de-assertion time
is 1 BCLK.
SYS_ERR_STAT[2:0]# O
Error output signals: Three signals per partition. Minimum assertion time is 12
cycles.
THERMTRIP# O
Thermal Trip: The processor protects itself from catastrophic overheating by use of
an internal thermal sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The processor will stop all
execution when the junction temperature exceeds approximately 125 C. This is
signaled to the system by the THERMTRIP# pin. See the appropriate platform
design guide for termination requirements.
Once activated, THERMTRIP# remains latched until RSTIN# is asserted. While the
assertion of the RSTIN# signal may de-assert THERMTRIP#, if the processor's
junction temperature remains at or above the trip level, THERMTRIP# will again be
asserted after RSTIN# is de-asserted.
Table 146. Power Signals (Sheet 1 of 2)
Signal Names
I/O
Type
Description
ISENSE Analog Current sense from VRD11.1 Compliant Regulator to the processor core.
VCC Analog
Processor core power supply. The voltage supplied to these pins is determined by
the VID pins.
VCC_SENSE Analog
VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the
processor core voltage and ground. They can be used to sense or measure voltage
near the silicon.
VCCPLL VCCPLL provides isolated power for internal processor PLLs.
VDDQ Processor I/O supply voltage for DDR3.
VID[7:0] I/O
VID[7:0] (Voltage ID) are used to support automatic selection of power supply
voltages (VCC). See the appropriate platform design guide or Voltage Regulator-
Down (VRD) 11.1 Design Guidelines for more information. The voltage supply for
these signals must be valid before the VR can supply VCC to the processor.
Conversely, the VR output must be disabled until the voltage supply for the VID
signals become valid. The VR must supply the voltage that is requested by the
signals, or disable itself.
VID7 and VID6 should be tied to Vss via a 1k resistor during reset (This value is
latched on the rising edge of VTTPWRGOOD).
VSS Analog
VSS are the ground pins for the processor and should be connected to the system
ground plane.
VSS_SENSE Analog
VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the
processor core voltage and ground. They can be used to sense or measure voltage
near the silicon.
VSS_SENSE_VTT Analog
VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection
to the processor VTT voltage and ground. They can be used to sense or measure
voltage near the silicon.
VTTA Analog Processor power for the memory controller, shared cache and I/O (1.1 V).
Table 145. Thermal Signals (Sheet 2 of 2)
Signal Names
I/O
Type
Description