Datasheet

Packaging and Signal Information
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
424 Order Number: 323103-001
12.1.7 Reset and Miscellaneous Signals
12.1.8 Thermal Signals
Table 144. Miscellaneous Signals
Signal Names
I/O
Type
Description
DP_SYNCRST# I/O
Dual Processor Synchronous Reset: signal driven from the legacy (boot) processor
to the non-legacy (application) processor. This signal is only needed for a dual
socket configuration.
COMP0 I Must be termianted on the system board using precision resistor.
EKEY_NC
Used to prevent damage to an unsupported processor if plugged into the platform.
No-Connect
EXTSYSTRG I/O External System Trigger. Debug trigger input mechanism.
PM_SYNC I
Power Management Sync: A sideband signal to communicate power management
status from the platform to the processor.
RSTIN# I
Reset In: When asserted this signal will asynchronously reset the processor logic.
This signal is connected to the PLTRST# output of the PCH.
DDR_ADR I
Asynchronous DRAM Refresh: When asserted this signal will cause the processor to
go into Asynchronous DRAM Refresh.
Table 145. Thermal Signals (Sheet 1 of 2)
Signal Names
I/O
Type
Description
CATERR# I/O
Catastrophic Error: This signal indicates that the system has experienced a
catastrophic error and cannot continue to operate. The processor will set this for
non-recoverable machine check errors or other unrecoverable internal errors.
PECI I/O
PECI (Platform Environment Control Interface) is the serial sideband interface to
the processor and is used primarily for thermal, power and error management.
Details regarding the PECI electrical specifications, protocols and functions can be
found in the Platform Environment Control Interface Specification.
PECI_ID# I
PECI client address identifier. Assertion (active low) of this pin results in a PECI
client address of 0x31 (versus the default 0x30 client address when pulled high).
This pin is primarily useful for PECI client address differentiation in DP platforms
and must be pulled up to VTT on one socket and down to VSS on the other. Single-
socket platforms should always pull this pin high.
DDR_THERM# I
External Thermal Sensor Input: If the system temperature reaches a dangerously
high value then this signal can be used to trigger the start of system memory
throttling.
PROCHOT# I/O
PROCHOT# will go active when the processor temperature monitoring sensor(s)
detects that the processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit has been activated, if
enabled. This signal can also be driven to activate the Thermal Control Circuit. This
signal does not have on-die termination and must be terminated on the system
board.