Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 423
Packaging and Signal Information
12.1.5 DMI / ESI Signals
12.1.6 Clock Signals
Table 142. DMI / ESI Signals
Signal Names
I/O
Type
Description
DMI_COMP I/O
DMI/ESI Configuration:
Pulled to Vss = ESI (AC coupling required).
Pulled to processor Vtt = DMI (DC coupling required).
Note: The processor and the PCH must both be configured appropriately to
support the same mode of operation.
DMI_PE_CFG# I/O
DMI/ESI or PCI Express Configuration:
No Connect = x4 interface set as DMI/ESI for the legacy (boot) processor. This
signal has an internal weak 10K pullup that’s activated for power on straps.
Pulled to Vss = x4 interface set as PCI Express (2.5 GT/s) on the non-legacy
(application) processor.
Note: DMI/ESI is not supported on the non-legacy (application) processor.
Note: PCI Express is not supported on the legacy (boot) processor.
DMI_PE_RX_DN[3:0]
DMI_PE_RX_DP[3:0]
I
DMI/ESI input from PCH: receive differential pair.
DMI is when DC coupling is used and DMI_COMP signal is set to DMI.
ESI is when AC coupling is used and DMI_COMP signal is set to ESI.
DMI_PE_TX_DN[3:0]
DMI_PE_TX_DP[3:0]
O
DMI/ESI output to PCH: Direct Media Interface transmit differential pair.
DMI is when DC coupling is used.
ESI is when AC coupling is used.
Table 143. PLL Signals
Signal Names
I/O
Type
Description
BCLK_BUF_DN
BCLK_BUF_DP
O Differential bus clock output from the processor. Reserved for possible future use.
BCLK_DN
BCLK_DP
I Differential bus clock input to the processor.
BCLK_ITP_DN
BCLK_ITP_DP
O Buffered differential bus clock pair to ITP.
PE_CLK_DN
PE_CLK_DP
I
Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock from an external clock
synthesizer. This clock is used to generate the clocks necessary for the support of
PCI Express and DMI.