Datasheet
Packaging and Signal Information
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
422 Order Number: 323103-001
12.1.3 PCI Express* Signals
12.1.4 Processor SMBus Signals
Table 140. PCI Express Signals
Signal Names
I/O
Type
Description
PE_CFG[2:0] I/O
PCI Express* Port Bifurcation Configuration:
111 = One x16 PCI Express I/O.
110 = Two x8 PCI Express I/O.
101 = Four x4 PCI Express I/O.
100 = Wait for BIOS to configure PCI Express I/O.
011 = One x8 (port 1-2) and two x4 PCI Express I/O.
010 = Two x4 and one x8 (port 3-4) PCI Express I/O.
001 = Reserved.
000 = Reserved.
PE_GEN2_DISABLE# I/O
PCI Express Gen2 Speed Disable: Will force Gen 1 (2.5 GT/s) negotiation across all
Processor PCI Express ports.
Note: Per port speed negiation via BIOS will not override this strap setting.
PE_ICOMPI Analog PCI Express current compensation.
PE_ICOMPO Analog PCI Express current compensation.
PE_NTBXL I/O
PCI Express Non-Transparent Bridge Cross Link Configuration.
The PE_NTBXL configuration is required when two processor’s PCI Express NTB
ports are connected together and configured as back to back NTB’s.
Note: For PE_NTBXL configuration via BIOS, board level strapping is not required
and the PE_NTBXL straps must be left as ‘No Connects” on each of the
processors.
PE_RBIAS Analog PCI Express resistor bias control.
PE_RCOMPO Analog PCI Express resistance compensation.
PE_RX_DN[15:0]
PE_RX_DP[15:0]
I PCI Express Receive differential pair.
PE_TX_DN[15:0]
PE_TX_DP[15:0]
O PCI Express Transmit differential pair.
Table 141. Processor SMBus Signals
Signal Names
I/O
Type
Description
PE_HP_CLK O PCI Express Hot Plug SMBus Clock.
PE_HP_DATA I/O PCI Express Hot Plug SMBus Address/Data.
SMB_CLK I/O SMBus Clock.
SMB_DATA I/O SMBus Address/Data.