Datasheet

Interfaces

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

42 Order Number: 323103-001

to receive inputs from a mirrored partner. If both channels fail simultaneously, an

uncorrectable error must be signaled. Mirror mode only recovers from a single error

(Resilvering is not supported).

2.1.3.6 Lockstep Mode

Lockstep Mode refers to splitting cache lines across channels. In this mode, the same

address is used on both channels, and an error on either channel is detected. The ECC

code used by the memory controller can correct 4 bits out of 72 bits. Since a single

DIMM is 72 bits wide (64 bits of data and 8 bits of ECC), in order to correct an entire x8

DRAM device, the 72 bit transfer is split across two channels. The IMC always (ECC

enabled or not) accumulates 32 bytes of data before forwarding to memory, therefore,

there is no latency penalty for enabling ECC. The correction capabilities in lockstep

mode are:

• Correction of any x4 or x8 DRAM device failure.

• Detection of 99.986% of all single bit failures that occur in addition to a x8 DRAM

failure. The Integrated Memory Controller will detect a series of failures on a

specific DRAM and use this information in addition to the information provided by

the code to achieve 100% detection of these cases.

• Detection of all permutations of two x4 DRAM failures.

Figure 4 shows where each bit of the ECC code appears in a pair of lockstepped

channels. The symbols are arranged so that the data from every x8 DRAM is mapped to

two adjacent symbols, so any failure of the DRAM can be corrected.

Figure 4 traces the bits of Data Symbol 0 (DS0) from DRAM. The lower nibble of the

symbol (DS0A) consists of DS0[3:0] and the upper nibble (DS0B) consists of DS0[7:4].

On the DRAM interface, DS0 is expanded to show that it occupies four DRAM lines for

two transfers. DS0[3:0] appears in the first transfer. DS0[7:4] appear in the second

transfer. DS0 and DS1 are the adjacent symbols that protect the eight lines from the

first DRAM on DIMM0.

Figure 4. Lockstep Code Layout