Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 419
Packaging and Signal Information
12.1.2 System Memory Interface
12.1.2.1 DDR Channel A Signals
Table 136. DDR Channel A Signals
Signal Names
I/O
Type
Description
DDRA_BA[2:0] O
Bank Address Select: These signals define which banks are selected within each
SDRAM rank.
DDRA_CAS# O
CAS Control Signal: Used with DDRA_RAS# and DDRA_WE# (along with
DDRA_CS#) to define the SDRAM commands.
DDRA_CKE[3:0] O
Clock Enable: (one per rank) used to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR.
DDRA_CLK_DN[3:0]
DDRA_CLK_DP[3:0]
O
SDRAM Differential Clock: Channel A SDRAM differential clock signal pair. The
crossing of the positive edge of DDRA_CLK_DPx and the negative edge of its
complement DDRA_CLK_DNx are used to sample the command and control
signals on the SDRAM.
DDRA_CS[7:0]# O
Chip Select: (one per rank) Used to select particular SDRAM components during
the active state. There is one chip-select for each SDRAM rank.
DDRA_DQ[63:0] I/O Data Bus: Channel A data signal interface to the SDRAM data bus.
DDRA_DQS_DN[17:0]
DDRA_DQS_DP[17:0]
I/O
Data Strobes: DDRA_DQS[17:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
DDRA_DQS_DP[17:0] and its DDRA_DQS_DN[17:0] during read and write
transactions. Different numbers of strobes are used depending on whether the
connected DRAMs are x4,x8 or have checkbits.
DDRA_ECC[7:0] I/O
Check Bits - An Error Correction Code is driven along with data on these lines for
DIMMs that support that capability.
DDRA_MA[15:0] O
Memory Address: These signals are used to provide the multiplexed row and
column address to the SDRAM.
DDRA_MA_PAR O Odd parity across address and command.
DDRA_ODT[3:0] O
On Die Termination: Active Termination Control.
Enables various combinations of termination resistance in the target and non-
target DIMMs when data is read or written.
DDRA_PAR_ERR[2:0]# I Parity Error detected by Registered DIMM (one per DIMM).
DDRA_RAS# O
RAS Control Signal: Used with DDRA_CAS# and DDRA_WE# (along with
DDRA_CS#) to define the SRAM commands.
DDRA_RESET# O
Resets DRAMs. Held low on power up, held high during self refresh, otherwise
controlled by configuration register.
DDRA_WE# O
Write Enable Control Signal: Used with DDRA_RAS# and DDRA_CAS# (along with
DDRA_CS#) to define the SDRAM commands.