Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 417
Reliability, Availability, Serviceability (RAS)
11.7.2.5.2 Attention Button
The IIO implements the attention button signal as an edge triggered signal, i.e. the attention button
status bit in the Slot Status register is set when an asserting edge on the signal is detected. If an
asserting edge on attention button is seen in the same clock, then software clears the attention
button status bit, the bit should remain set and if MSI is enabled, another MSI message should be
generated.
Also, debounce logic on the attention button signal is to be implemented on the board.
11.7.2.5.3 Power Fault
IIO implements the Power Fault signal as a level signal with the following property. When the signal
asserts, the IIO sets the Power Fault status bit in the Slot Status register (and a 0->1 edge on the
status bit would cause an MSI interrupt, if enabled). When software clears the status bit, IIO re-
samples the power fault signal and if it is still asserted, the status bit is set once more and it triggers
one more MSI interrupt, if enabled.
11.7.3 Intel
®
QPI Hot Plug
The Intel
®
Xeon
®
processor C5500/C3500 series does not support Intel
®
QPI Hot Plug.
§ §