Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
416 Order Number: 323103-001
11.7.2.5 Miscellaneous Notes
11.7.2.5.1 VPP Port Reset
The VPP port logic in the IIO is reset immediately when a PWRGOOD reset happens. When a hard
reset happens, the IIO internally delays resetting the VPP logic until the currently running transaction
on the VPP port reaches a logical termination point, i.e. reaches a transaction boundary. Then the VPP
logic is reset within a timeout. This delayed reset of VPP logic guarantees that the VPP port is not
hung after reset, which can happen if a transaction was terminated randomly while the VPP device
like PCA9555 was still actively listening on the bus while IIO is being reset. The rest of the IIO could
be in reset while the VPP port is still active. After a hard reset, IIO would start activity on the VPP port
provided the VPP port was configured before hard reset was asserted. This is because the VPP port
control registers are all sticky.
Some caveats relating to VPP port reset:
If the Powergood signal was toggled without actually removing power, there is a potential to still
hang the VPP port since the VPP device would not be reset whereas IIO would be:
The board needs to work around this issue by not toggling powergood without removing
power to PCA9555 (a FET on the power input to PCA9555 that is controlled by powergood
would do the trick).
There is a potential that the EMIL signal remains stuck at 1 if the IIO is reset in the middle of
pulsing that signal. This can potentially cause malfunction of the electro-mechanical latch. To
prevent that board must AND the EMIL output of IIO with the appropriate reset signal before
feeding to the latch.
Table 134. Read Command
Bits IIO Drives IO Port Drives Comment
1 Start SDL falling followed by SCL falling
7 Address[6:0]
[6:3] = 0100
[2:0] = “VPPCTL: VPP Control”
1 0 indicates write
1ACK
If NACK is received, IIO completes with stop and sets in
“VPPSTS: VPP Status Register”.
8Command Code
Register Address
[2:0] = 000
1ACK
If NACK is received, IIO completes with stop and sets in
“VPPSTS: VPP Status Register”.
1 Start SDL falling followed by SCL falling
7 Address[6:0]
[6:3] = 0100
[2:0] = “VPPSTS: VPP Status Register”
1 1 indicates read
8Data
One bit for each IO as per Table 132. The IIO always reads
from both ports. Results for invalid VPPs are discarded
1ACK
8Data
One bit for each IO as per Table 132. The IIO always reads
from both ports. Results for invalid VPPs are discarded
1NACK
1Stop