Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 415
Reliability, Availability, Serviceability (RAS)
Table 133 describes the sequence generated for a write to an IO port. Both 8-bit ports are always
written. If a VPP is valid for the 8-bit port, the Output values are updated as per the PCIe Slot Control
register for the associated PCIe slot.
The IIO issues Read Commands to update the PCIe Slot Status register from the I/O port. The I/O
port requires that a command be sent to sample the inputs, then another command is issued to
return the data. The IIO always reads inputs from both 8-bit ports. If the VPP is valid, then the IIO
updates the associated PEXSLOTSTS (for PCIe) register according to the values of MRL/EMLSTS#,
BUTTON#, PWRFLT# and PRSNT# read from the value register in the IO Port. Results from invalid
VPPs are discarded. Table 134 defines the read command format.
Bit 5 Input Low_True PWRFLT#
PWR Fault in the
VRM
NO PWR Fault in the
VRM
Bit 6 Input High_True MRL/EMILS
MRL is open/EMILS
is disengaged
MRL is closed/EMILS
is engaged
Bit 7 Output High_True EMIL
Toggle interlock
state -Pulse output
100ms when ‘1’ is
written
No effect
Table 133. Write Command
Bits IIO Drives IO Port Drives Comment
1 Start SDL falling followed by SCL falling
7 Address[6:0]
[6:3] = 0100
[2:0] = “VPPCTL: VPP Control”
1 0 indicates write
1ACK
If NACK is received,
IIO completes with stop and sets
status bit in “VPPSTS: VPP Status Register”.
8 Command Code
Register Address see Table 131
[7:3]=00000,[2:1] = 01 for Output, 11 for Direction
[0] = 0
1ACK
If NACK is received,
IIO completes with stop and sets in
“VPPSTS: VPP Status Register”.
8 Data One bit for each IO as per Table 132
1ACK
If NACK is received,
IIO completes with stop and sets in
“VPPSTS: VPP Status Register”.
8 Data One bit for each IO as per Table 132
1ACK
If NACK is received,
IIO completes with stop and sets in
“VPPSTS: VPP Status Register”.
1Stop
Table 132. Hot Plug Signals on a Virtual Pin Port (Sheet 2 of 2)
Bit Direction
Voltage Logic
Table
Signal
Logic True
Meaning
Logic False
Meaning