Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
414 Order Number: 323103-001
The IIO VPP only supports SMBus devices with the command sequence shown Table 131. Each PCIe
port is associated with one of these 8-bit ports. The mapping is defined by a Virtual Pin Port register
field for each PCIe slot. The VPP register holds the SMBus address and Port (0 or 1) of the I/O port
associated with the PCIe. A[1:0] pins on each I/O extender (i.e. PCA9555) connected to the IIO must
be strapped uniquely.
11.7.2.4 Operation
When the Intel
®
Xeon
®
processor C5500/C3500 series IIO comes out of Powergood reset, the I/O
ports are inactive. The IIO is not aware of how many I/O extenders are connected to VPP, what their
addresses are, nor what PCIe port are hot-pluggable. The IIO does not master any commands on the
SMBus until one VPP enable bit is set.
For a PCI Express slot, an additional FF (Form Factor) bit (see “MISCCTRLSTS: Misc. Control and
Status Register6”) is used to differentiate card, module or cable hotplug support. When the BIOS sets
the VPP Enable bit (see “VPPCTL: VPP Control”), the IIO initializes the associated VPP corresponding
to that root port with direction and logic Level configuration. From then on, the IIO continually scans
in the inputs corresponding to that port and scans out the outputs corresponding to that port. VPP
registers for PCI Express ports that do not have the VPP enable bit set are invalid and ignored.
Table 132 defines how the eight hot-plug signals are mapped to pins on the I/O extender’s GPIO pins.
When the IIO is not doing a direction or logic level write, which would happen when a PCIe port is first
setup for hot plug, it performs input register reads and output register writes to all valid VPPs. This
sequence repeats indefinitely until a new VPP enable bit is set. To minimize the completion time of this
sequence and to reduce logic complexity, both ports in the external device are written or read in any
sequence. If only one port of the external device has yet been associated with a hotplug capable root
port, the value read from the other port of the external device are throw away and only de-asserted
values are shifted out for the outputs (see Table 132
for the list of output signals and their polarity).
Table 131. I/O Port Registers in On-Board SMBus devices Supported by IIO
Command Register IIO Usage
0 Input Port 0
Continuously Reads Input Values
1 Input Port 1
2Output Port 0
Continuously Writes Output Values
3Output Port 1
4 Polarity Inversion Port 0
Never written by
IIO
5 Polarity Inversion Port 1
6 Configuration Port 0
Direction (Input/Output)
7 Configuration Port 1
Table 132. Hot Plug Signals on a Virtual Pin Port (Sheet 1 of 2)
Bit Direction
Voltage Logic
Table
Signal
Logic True
Meaning
Logic False
Meaning
Bit 0 Output High_True ATNLED
ATTN LED is to be
turned ON
ATTN LED is to be
turned OFF
Bit 1 Output High_True PWRLED
PWR LED is to be
turned ON
PWR LED is to be
turned OFF
Bit 2 Output Low_True PWREN#
Power is to be
enabled on the slot
Power is NOT to be
enabled on the slot
Bit 3 Input Low_True BUTTON#
ATTN Button is
pressed
ATTN Button is NOT
pressed
Bit 4 Input Low_True PRSNT# Card Present in slot
Card NOT Present in
slot