Datasheet
Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
408 Order Number: 323103-001
11.7 Hot Add/Remove Support
The Intel
®
Xeon
®
processor C5500/C3500 series has hot add/remove support for PCIe devices. This
feature allows physical hot plug/removal of a PCIe device connected to the processor IIO. In addition,
physical hot add/remove for other IO devices downstream to the IIO may be supported by
downstream bridges. Hot plug of PCIe and IO devices are defined in the PCIe/PCI specifications.
DC
IIO SAD illegal or
non-existent
memory for
outbound snoop
2
Drop Transaction,
No Response. This will cause
time-out in the requester for
non-posted requests. (e.g.
completion time-out in Intel
®
QPI request agent, or PCIe
request agent.)
FERR/NERR is logged in Intel
®
QPI and Global Fatal
Error Log Registers:
QPIPFFERRST
QPIPFFERRHD
QPIPFNERRST
GFERRST
GFFERRST
GFFERRTIME
GFNERRST
Intel
®
QPI header is logged
DE
IIO Routing Table
pointed to a
disabled Intel
®
QPI port
DF
Illegal inbound
request (includes
VCp/VC1 request
when they are
disabled)
DG
Intel
®
QPI Link
Layer detected
unsupported/
undefined packet
(e.g., RSVD_CHK,
message class,
opcode, vn, viral)
Note: do not
support Viral Alert
Generation
2
No Response -- This error is not
associated with a cycle. IIO
detects and logs the error.
FERR/NERR is logged in Intel
®
QPI and Global Fatal
Error Log Registers:
QPIFFERRST
QPIFNERRST
GFERRST
GFFERRST
GFFERRTIME
GFNERRST
No header logged for this error
DH
Intel
®
QPI
Protocol Layer
Detected
unsupported/
undefined packet
Error (message
class, opcode and
vn only) -
2
No Response -- This error is not
associated with a cycle. IIO
detects and logs the error.
FERR/NERR is logged in Intel
®
QPI Protocol and
Global Fatal Error Log Registers:
QPIPFFERRST
QPIPFNERRST
GFERRST
GFFERRST
GFFERRTIME
GFNERRST
1. This column notes the logging registers used assuming the error severity default remains. The error’s severity dictates the actual
logging registers used upon detecting an error.
2. IIO does not detect any Intel
®
QuickData Technology DMA unaffiliated errors and hence these errors are not listed in the
subsequent DMA error discussion
3. It is possible that when a UR response is returned to the original requester, the error is logged in the AER of the root port
connected to the requester.
4. In some cases, IIO might not be able to log the error/header in AER when it signals UR back to the PCIe device.
5. It is possible that when a CA response is returned to the original requester, the error is logged in the AER of the root port
connected to the requester.
6. In some cases, IIO might not be able to log the error/header in AER when it signals CA back to the PCIe device.
7. Not all cases of this error are detected by IIO.
8. If error is detected too late for IIO to drop the packet internally, it needs to ‘EDB’ the transaction.
Table 129. IIO Error Summary (Sheet 15 of 15)
ID Error
Default
Error
Severity
Transaction Response Default Error Logging
1