Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
40 Order Number: 323103-001
2.1.3.4 Spare Channel Mode
In this mode, channels A and B operate as independent channels, with channel C
functioning as a spare should either channels A or B fail. When ECC is used, error
correction/detection on a single channel is the same as provided by Independent
Channel Mode. The IMC initiates a sparing copy from a failed channel to the spare
channel, or the SW can initiate a sparing copy if a specific channel is experiencing a
high rate of correctable errors.
The Integrated Memory Controller will maintain correctable ECC error counters for each
DIMM in the system that can either trigger an SMI event or be periodically polled by
software to determine whether a high error rate is happening. Software can then
configure the Integrated Memory Controller to copy contents from one channel to
another.
While performing a sparing copy, the Integrated Memory Controller operates as
follows:
• When software initiates a Sparing operation, the Integrated Memory Controller
copies data from one channel to the other. The SS (Sparing/Scrub) engine
performs operations in the DRAM Address space indicated by DA(x), where x is a
system address.
• Software controls entry into this mode by disabling scrubbing and writing the SSR
control register with source and destination channel IDs.
• If the operation succeeds without uncorrectable error, the Integrated Memory
Controller will set the SSR Copy Complete (CMPLT) bit in the MC_SSRSTATUS
register.
• System memory writes are duplicated to each channel while data is copied from the
channel specified by the SRC_CHAN parameter to the channel specified by the
DEST_CHAN parameter in the MC_SSRCONTROL register.
Figure 3. Independent Code Layout
DS0
[1]
DS0
[0]
DRAM pins DQ[0]DQ[1]DQ[2]DQ[3]
x
4
DIMM Channel 1
DQ[71:0]
CB
[7:0]
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
x
4
DS0
[2]
DS0
[3]
D[3] D[2] D[1] D[0]
DS0
[4]
DS0
[5]
DS0
[6]
DS0
[7]
D[131] D[130] D[129] D[128]
D
S
0
A
D
S
1
A
D
S
3
A
D
S
5
A
D
S
7
A
D
S
9
A
D
S
1
1
A
D
S
1
3
A
D
S
1
5
A
C
S
1
A
C
S
0
A
D
S
1
B
D
S
3
B
D
S
5
B
D
S
7
B
D
S
9
B
D
S
1
1
B
D
S
1
3
B
D
S
1
5
B
C
S
1
B
C
S
0
B
C
S
3
A
C
S
2
A
D
S
2
0
A
D
S
1
9
A
D
S
2
1
A
D
S
1
8
A
D
S
2
4
A
D
S
2
3
A
D
S
2
5
A
D
S
2
2
A
D
S
2
8
A
D
S
2
7
A
D
S
2
9
A
D
S
2
6
A
D
S
3
1
A
D
S
3
0
A
D
S
1
7
A
C
S
3
B
C
S
2
B
D
S
2
0
B
D
S
1
9
B
D
S
2
1
B
D
S
1
8
B
D
S
2
4
B
D
S
2
3
B
D
S
2
5
B
D
S
2
2
B
D
S
2
8
B
D
S
2
7
B
D
S
2
9
B
D
S
2
6
B
D
S
3
1
B
D
S
3
0
B
D
S
1
7
B
D
S
2
A
D
S
6
A
D
S
4
A
D
S
1
0
A
D
S
8
A
D
S
1
4
A
D
S
1
2
A
D
S
2
B
D
S
0
B
D
S
6
B
D
S
4
B
D
S
1
0
B
D
S
8
B
D
S
1
4
B
D
S
1
2
B
D
S
1
6
A
D
S
1
6
B
Transfer 0
Transfer 1
Transfer 2
Transfer 3
Symbol on DRAM pins