Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
398 Order Number: 323103-001
62
DMA configuration
register parity
error
2
N/A since the error is not
associated with a specific
transaction.
Log the error in corresponding DMAUNCERRSTS/
DMAUNCERRPTR registers and also DMAGLBERRPTR
register.
If error is forwarded to the global error registers, it is
logged in global fatal log registers:
GFERRST
GFFERRST
GFFERRTIME
GFNERRST
63
DMA
miscellaneous fatal
errors (lock
sequence error
etc.)
PCIe/DMI Errors
70
PCIe Receiver
Error
0
Respond per PCIe specification
Log error per PCI Express AER requirements for
these correctable errors/message.
Log in XPGLBERRSTS, XPGLBERRPTR registers.
If PCIe correctable error is forwarded to the global
error registers, it is logged in global non-fatal log
registers - GNERRST, GNFERRST, GNNERRST,
GNFERRTIME.
71 PCIe Bad TLP
72 PCIe Bad DLLP
73
PCIe Replay Time-
out
74
PCIe Replay
Number Rollover
75
Received
ERR_COR
message from
downstream
device
76
PCIe Link
Bandwidth
changed
No Response. This error is not
associated with a cycle. IIO
detects and logs the error.
Log per ‘Link bandwidth change notification
mechanism’ ECN.
Log in XPCORERRSTS register.
Log in XPGLBERRSTS, XPGLBERRPTR registers.
If error is forwarded to the global error registers, it is
logged in global non-fatal log registers - GNERRST,
GNFERRST, GNNERRST, GNFERRTIME.
77
PCIe ECC
correctable error
(PCIe cluster
detected internal
ECC correctable
error)
Log in XPCORERRSTS register.
Log in XPGLBERRSTS, XPGLBERRPTR registers.
If error is forwarded to the global error registers, it is
logged in global non-fatal log registers - GNERRST,
GNFERRST, GNNERRST, GNFERRTIME.
Table 129. IIO Error Summary (Sheet 5 of 15)
ID Error
Default
Error
Severity
Transaction Response Default Error Logging
1