Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 397
Reliability, Availability, Serviceability (RAS)
DMA Errors
2
40
DMA Transfer
Source Address
Error
1
IIO halts the corresponding DMA
channel and aborts the current
channel operation.
Log the error in corresponding CHANERRx_INT/
CHANERRPTRx registers and also DMAGLBERRPTR
register.
If error is forwarded to the global error registers, it is
logged in global non-fatal log registers:
GNERRST
GNFERRST
GNFERRTIME
GNNERRST
41
DMA Transfer
Destination
Address Error
42
DMA Next
Descriptor Address
Error
43
DMA Descriptor
Error
44
DMA Chain
Address Value
Error
45
DMA CHANCMD
Error
46
DMA Chipset
Uncorrectable
Data Integrity
error (i.e. DMA
detected
uncorrectable data
ECC error)
47
DMA Uncorrectable
Data Integrity
error (i.e. DMA
detected
uncorrectable data
ECC error)
48
DMA Read Data
Error
49
DMA Write Data
Error
4A
DMA Descriptor
Control Error
4B
DMA Descriptor
Length Error
4C
DMA Completion
Address Error
4D
DMA Interrupt
Configuration
Errors - a) MSI
address not equal
to 0xFEEx_xxxx b)
writes from non-
MSI sources to
0xFEEx_xxxx
4E
DMA CRC or XOR
error
Table 129. IIO Error Summary (Sheet 4 of 15)
ID Error
Default
Error
Severity
Transaction Response Default Error Logging
1