Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
394 Order Number: 323103-001
Table 128. IIO Default Error Severity Map
Error
Severity
IIO Intel
®
QPI PCIe
Inband Error Reporting
(Programmable)
0
Hardware
Correctable Error
Hardware
Correctable Error
Correctable Error.
NMI/SMI/CPEI
IIO default: CPEI
1 Recoverable Error Recoverable Error Non-Fatal Error.
NMI/SMI/CPEI
IIO default: CPEI
2 Fatal Error Unrecoverable Error Fatal Error
NMI/SMI/CPEI
IIO default: SMI
Table 129. IIO Error Summary (Sheet 1 of 15)
ID Error
Default
Error
Severity
Transaction Response Default Error Logging
1
IIO Core Errors
11
IIO access to non-
existent address
(Internal datapath
coarse address
decoders are
unable to decode
the target of the
cycle).
1
For PCIe and Intel
®
QPI initiated
transactions. This case includes
snoops from Intel
®
QPI. A
master abort convert to normal
responses on Intel
®
QPI and
additionally returning a data of
all Fs on reads.
SMBus to IIO accesses requests:
The IIO returns UR status on
SMBus.
FERR/NERR is logged in the IIO Core and Global Non-
Fatal Error Log Registers:
IIONFERRST
IIONFERRHD
IIONFERRSYN
IIONNERRST
GNERRST
GNFERRST
GNFERRTIME
GNNERRST
IIO core header is logged.
12
Intel
®
QPI
transactions that
cross 64B
boundary.
1
Intel
®
QPI read: IIO returns all
‘1s’ and normal response to
Intel
®
QPI to indicate master
abort.
Intel
®
QPI write: IIO returns
normal response and drops the
write data.
PCIe read: Completer Abort is
returned on PCIe.
PCIe non-posted write:
Completer abort is returned on
PCIe. The write data is dropped
PCIe posted write: IIO drops the
write data.
SMBus to IIO accesses requests:
IIO returns CA status on SMBus.
FERR/NERR is logged in IIO Core and Global Non-
Fatal Error Log Registers:
IIONFERRST
IIONFERRHD
IIONNERRST
GNERRST
GNFERRST
GNFERRTIME
GNNERRST
IIO core header is logged.