Datasheet
Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
390 Order Number: 323103-001
3. The local FERR and NERR logging events are forwarded to the global FERR and NERR registers.
The report of local FERR/NERR sets the corresponding global error bit if the global error is
enabled; otherwise the global error bit is not set and the error is forgotten. The global FERR logs
the first occurrence of local FERR/NERR event in the IIO and the global NERR logs the subsequent
local FERR/NERR events.
4. Severity 0 and 1 are logged in the global Non-Fatal FERR/NERR registers and severity 2 is logged
in the global Fatal FERR/NERR registers.
5. Global error register reports errors with associated error severity to the system event status
register. The system event status is set if the system event reporting is enabled for error severity;
otherwise the bit is not set and error is not reported.
6. Setting the system event bit triggers a system event generation according mapping defined in the
system event map register. An associated system event is generated for the error severity and
dispatched to CPU/BMC of the error (interrupt for CPU or error pin for BMC).
7. The global and local log registers provide information to identify source of the error. Software can
read the log registers and clear the global and local error status bits.
8. Since error status bits are edge-triggered, 0 to 1 transition is required for bit reset. While the
error status bit (local, global, or system event) is set to 1, all incoming error reporting to
respective error status register are ignored (no 0 to 1 transition).
a. When write to clear the local error status bit, the local error register re-evaluates the OR output
of its error bits and reports it to the global error register. However, if the global error bit is
already set, then the report is ignored.
b. When write to clear error status bit, the global error register re-evaluates the OR output of its
error bits and reports it to the system event status register. However, if the system event status
bit is already set, then the report is not generated.
c. Software can optionally mask or unmask the system event generation (interrupt or error pin)
for an error severity in the system event control register while clearing the local and global
error registers.
9. Software has the following options for clearing error status registers:
a. Read global and local log registers to identify the source of errors. Clear local error bits. This
does not cause generation of an interrupt with global bit still set. Then, clear the global error
bit and write 0s (zeros) to the local error register. Writing 0s to the local status does not clear
any status bit, but causes a re-evaluation of the error status bits. An error will be reported if
there is any unclear local error bit.
b. Read the global and local log registers to identify the source of the error and mask the error
reporting for the error severity. Clear system event and global error status bits. This causes
setting of the system event status bit if there are other global bits still set. Then clear local
error status bits. This causes setting of the global error status bit if there are other local error
bits still set. Then, unmask system event to cause the IIO to report the error.
10.FERR logs the information for the first error detected by the associated error status register (local
or global). The FERR log remains unchanged until all bits in the respective error status register
are cleared by software. When all error bits are cleared, then FERR logging is re-enabled.
11.3.3.6 Error Containment
The IIO attempts to isolate and contain errors. For structures that can be contained, the error
detected by the structure reports errors.
The IIO also provides an optional mode in which poisoned data received from either Intel
®
QuickPath
Interconnect or peer PCI Express port is never sent out on PCI Express. I.e. any packet with poisoned
data is dropped internally in by the IIO and an error is generated.