Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 39
Interfaces
2.1.3.2 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when only a single channel is populated with memory.
2.1.3.3 Independent Channel Mode
In this mode one, two, or all three channels operate independently. Each channel stores
one complete cache line per transfer. When ECC is used with x4 DRAM devices, a failure
of an entire x4 DRAM device can be corrected, x8 DRAMs can also be used but not all
bit failures can be corrected, and x8 device failures are not correctable. The correction
capabilities in independent mode are:
• Correction of any x4 DRAM device failure.
• Detection of 99.986% of all single bit failures that occur in addition to a x4 DRAM
failure.
• Detection of all 2-bit uncorrectable errors.
This mode supports the most flexibility with respect to DIMM populations, and
bandwidth performance.
Figure 3 shows how the symbols are mapped to DRAM bits on the DIMM for a transfer
in which the critical 16 B is in the lower half of the codeword (A[4]=0). If the upper
portion of the codeword were transferred first, bits[7:4] of each symbol would be
transferred first on the DRAM interface.
The lower nibble of the symbol (DS0A) consists of DS0[3:0] and the upper nibble
(DS0B) consists of DS0[7:4]. On the DRAM interface, DS0 is expanded to show that it
occupies 4 DRAM lines for two transfers. DS0[3:0] appear in the first transfer. DS0[7:4]
appear in the second transfer. DS0 and DS1 are the adjacent symbols that protect all
four transfers in the codeword on the four lines from the first DRAM on DIMM0.
Table 10. Mapping from Logical to Physical Channels
Channel Mode Mirroring Logical to Physical
Independent Channels
Disabled 1:1 relationship, but may not be the same number.
Enabled
A pair of physical channels are combined to form a single logical
redundant channel. Requests to logical channel A are handled by
physical channels A and B.
Lockstep Disabled
A pair of physical channels are accessed in parallel to form a
single logical channel. Lockstep of arbitrary physical channels is
not supported. Physical channel A provides half of the data for
each request to Logical Channel A. Physical channel B provides
the other half.