Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 389
Reliability, Availability, Serviceability (RAS)
11.3.3.5 Error Registers Flow
1. Upon a detection of an unmasked local error, the corresponding local error status is set if the error
is enabled; otherwise the error bit is not set and the error is forgotten.
2. The local error is mapped to its associated error severity defined by the error severity map
register. Setting the local error status bit causes the logging of the error. Severity 0, 1, and 3 is
logged in the local Non-Fatal FERR/NERR registers and severity 2 is logged in the local Fatal FERR/
NERR registers. PCIe errors are logged according to the PCIe specification.
Figure 79. IIO Error Logging Flow
Update Global
FERR
Registers
Update Global
FERR
Registers
Local
FERR in use?
No
Yes
Update Local
FERR
Registers
Update Local
NERR
Registers
Local
Error Masked
?
Yes
No
First
Local
Error?
Done
Set Local Error
Status Bit
Update Local
FERR
Registers
Update Local
NERR
Registers
Report Error
Severity to
Global Error
Global
Error Masked
?
No
No
Set Global
Error Status for
The Error
Severity
Yes
Update Global
FERR
Registers
Update Gobal
NERR
Registers
Local
Error
Yes
Done
First
Global
Error?
Map Error Severity to
Programmed System Event.
Separate logging to Global
Fatal and Global Non-Fatal
Generate
System
Event
Map Error to Programmed
Severity.
Separate logging to Local
Fatal and Local Non-Fatal
Fatal Non-Fatal Non-FatalFatal