Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 387
Reliability, Availability, Serviceability (RAS)
Figure 78 shows the logic diagram of the IIO local and global error registers.
Figure 78. Error Logging and Reporting Example
Error Severity Map Reg
Local Error Enable Reg
E
r
r
Src
0
E
r
r
Src
1
Err Src n
Local Fatal FERR
Local Non-Fatal FERR
Local Error Status Reg
Severity 0
System Event Status Reg
System Event Mask
Reg
System Event Map Reg
CPEI SMI NMI
Global Fatal FERR
Global Non-Fatal FERR
Error Event
(Pulse)
Read Only Sticky
RW1CS Event/Edge
Triggered Flops
Local Fatal
Errors
Local Non-Fatal
Errors
Read Only Sticky
Level Flops
Severity 0
Severity 2
Global Fatal
ErrorStatus Reg
Global Error Mask Reg
Read Only Sticky
Global Non-Fatal
ErrorStatus Reg
RW1CS Event/Edge
Triggered Flops