Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 385
Reliability, Availability, Serviceability (RAS)
then an SMI is dispatched to the CPU and IIO error[2] is asserted. The CPU or BMC can read the
Global and Local Error Log register to determine where the error came from and how it should
handle the error.
At power-on reset, these register are initialized to their default values. The default mapping of
severity and system event is set to be consistent with Table 129. Firmware can choose to use the
default values or modify the mapping according to the system requirements.
The system event control register is non-sticky register that is cleared by hard reset.
Figure 77 shows an example how an error is logged and reported to the system by the IIO.
Figure 76. IIO System Event Register
Corretable Error
Fatal Error
No
n
-Fatal Error
Errors from the
global error registers
are catagorized to 3
error severities
Each Error Severity
can be masked
Mask
3
Mask
1
Mask
2
System Event 3
System Event 1
System Event 2
Error Severity
2
Error Severity
0
Error Severity
1
Mask
2
Mask
0
Mask
1
System Event 2
System Event 0
System Event 1
Each Error Severity can map to:
SMI
NMI
CPEI
None
and/or Error Pin
System Event
Status Reg
System
Event
Control Reg
System Event
Map Reg
Error Severity from
Global Error Status
System
Event