Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 383
Reliability, Availability, Serviceability (RAS)
• Local Error Severity Register
The IIO core provides a local error severity register for the errors associated with the IIO core
itself. IIO internal errors can be mapped to three error severity levels. Intel
®
QuickPath
Interconnect and PCIe error severities are mapped according to Table 128.
• Local Error Log Register
The IIO core provides a local error log register for errors associated with the IIO component itself.
When the IIO detects an error, the information related to the error is stored in the log register.
IIO core errors are first separated into Fatal and Non-Fatal (Correctable, Recoverable) categories.
Each category contains two sets of log registers: FERR and NERR. FERR logs the first occurrence
of an error and NERR logs the subsequent occurrences. However, NERR does not log header/
address or ECC syndrome. FERR/NERR does not log a masked error. FERR log remains valid and
unchanged from the first error detection until the clearing of the corresponding FERR error bit in
the error status register by the software. The **ERRST registers are only cleared by writing to
the.corresponding local error status register. For example, clearing bit 0 in QPIPERRST0 clear the
bit in this register as well as bit 0 in: QPIPFFERRST0, QPIPFNERRST0, QPINFERRST0,
QPINNERRST0.
11.3.3.2 Global Error Registers
Global error registers collect errors reported by local interface and convert the errors to system
events.
• Global Error Control/Status Register
The IIO provides two global error status register to collect errors reported by the IIO clusters:
Global Fatal Error Status and Global Non-fatal Error Status. Each register has an identical format
that each bit in the register represents the fatal or non-fatal error reported by its associated
interface: the Intel
®
QuickPath Interconnect port, PCIe port, DMA, or IIO core logic.
Figure 74. IIO Core Local Error Status, Control and Severity Registers
Each error can be
controlled/masked by
the associated error
control register bit
Each error can be
mapped to one of three
severities by the Error
Severity Reg
Datapath Correctable ECC
Header Parity Error
Other IIO errors
Write Cache UC ECC
Datapath UC ECC
Mask N
Mask A
Severity N
When IIO detects an error, it is
indicated in the associated error
status bit in the error status reg
Severity D
Severity C
Severity B
Severity A
Mask B
Mask C
Mask D
Error Status
Register
Error Control
Register
Error Severity
Register
Error Event
from Local
Interface
Error Severity
to Global Error
Registers