Datasheet

Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
382 Order Number: 323103-001
11.3.3.1 Local Error Registers
Each IIO local interface contains a set of local error registers. PCIe ports (including DMI) local error
registers are defined per the PCIe specification. The Intel
®
QuickData Technology DMA has a
predefined set of error registers. See the PCIe specifications for more details.
Since Intel
®
QuickPath Interconnect has not defined a set of standard error registers, the IIO has
defined the error registers for the Intel
®
QuickPath Interconnect port using the same error control
and report mechanism as the IIO core. This is described as follows:
• IIO Local Error Status Register
The IIO core provides the local error status register for the errors associated with the IIO
component itself. When a specific error occurred in the IIO core, its corresponding bit in the error
status register is set. Each error can be individually masked by the error control register.
• IIO Local Error Control (Mask) Register
The IIO core provides the local error control/mask register for the errors associated with the IIO
component itself. Each error detected by the local error status register can be individually masked
by the error control register. If an error is masked, the corresponding status bit will not be set for
any subsequent detected error. The error control register is non-sticky and is cleared upon hard
reset (all errors are masked). Figure 74 illustrates the IIO core Error Control/Status Register.
Figure 73. IIO Error Registers
PCI-E
Local Error
Status
Control Reg
Local Error
Severity
Reg
CPEI
NMI
SMI
Local Error
Log Register
Error Pin
Global Error
Log Reg
Global Error
Status
Control Reg
System
Event Reg
IIO
Core
PCI- E Error
Control/Status
PCI- E Error
Severity
Intel® QPI
Intel® QPI
Error
Control/Status
Intel® QPI
Error
Severity
MSI
Per PCI- E Specification
IIO Global
Error Registers
IIO Local
Error Registers