Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 381
Reliability, Availability, Serviceability (RAS)
11.3.2.2.7 PCIe/DMI “Stop and Scream”
There is a enable bit per PCIe port that controls “stop and scream” mode. In this mode the desire is to
disallow sending poisoned data onto PCIe and instead disable the PCIe port that was the target of
poisoned data. This is done because in the past there have been PCIe/DMI devices that have ignored
the poison bit and committed the data that can corrupt the I/O device.
11.3.2.2.8 PCIe “Live Error Recovery”
PCI Express ports support the Live Error Recover (LER) mode. When errors are detected by the PCIe
port, the PCIe port goes into a Live Error Recovery mode. When a root port enters the LER mode it
brings down the associated link and automatically trains the link up.
11.3.3 IIO Error Registers Overview
The IIO contains a set of error registers (Device 8, Function 2) to support error reporting.
Global Error registers
Local Error registers
IIO System Control Status registers
These error registers are assumed to be sticky unless specified otherwise. Sticky means the values of
the registers are retained even after a hard reset —they can only be cleared by software or by power-
on reset.
There are two levels of hierarchy for the error registers: local and global. The local error registers are
associated with the IIO local clusters (e.g. PCIe, DMI, Intel
®
QuickPath Interconnect, DMA, and IIO
core logic). The global error registers collect the errors reported by the local error registers and map
them to system events. Figure 73 illustrates the high level view of the IIO error registers. Figure 74
through Figure 79 illustrate the function of each error register.