Datasheet
Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
380 Order Number: 323103-001
11.3.2.2.1 NMI (Non-Maskable Interrupt)
In past platforms, NMI reported fatal error conditions, typically through PCH component SERR
mapping. Since the IIO provides direct mapping of an error to NMI, SERR reporting is obsolete. When
an error triggers an NMI, the IIO broadcasts an NMI virtual legacy wire cycle to the CPUs. The PCH
reports the NMI through assertion of the NMI pin. The IIO converts the NMI pin assertion to the Intel
®
QuickPath Interconnect legacy wire cycle on behalf of the PCH.
11.3.2.2.2 CPEI (Correctable Platform Event Interrupt)
CPEI is associated with a PCH component, programmed interrupt vector. When CPEI is needed for
error reporting, the non-legacy IIO is configured to send the CPEI message to the legacy IIO. The
message converts in the legacy IIO to Error[2:0] pin assertion conveying the CPEI event when
enabled. As a result, the PCH sends a CPU interrupt with the specific interrupt vector and type defined
for CPEI.
11.3.2.2.3 SMI (System Management Interrupt)
SMI reports fatal and recoverable error conditions. When an error triggers an SMI, the IIO broadcasts
a SMI legacy wire cycle to the CPUs.
11.3.2.2.4 None
The IIO provides the flexibility to disable inband messages on the detection of an error. By disabling
the inband messages and enable error pins, the IIO can be configured to report the errors exclusively
via error pins.
11.3.2.2.5 Error Pins
The IIO contains three open-drain error pins for the purpose of error reporting — one pin for each
error severity. The error pin can be used in a certain class of platforms to indicate various error
conditions and can also be used when no other reporting mechanism is appropriate. For example, an
error signal can be used to indicate error conditions (even hardware correctable error conditions) that
may require error pin assertion to notify outband components, such as the BMC.
In some extreme error conditions when inband error reporting is no longer possible, the error pins
provide a way to inform the outband agent of the error. Upon detecting error pin assertion, the
outband agent interrogates various components in the system and determines the health state of the
system. If the system can be gracefully recovered without reset, then the BMC performs steps to
return the system to a functional state. However, if the system is unresponsive, then the outband
agent can assert reset to force the system back to a functional state.
The IIO allows the software to enable/disable error pin assertion upon the detection of the associated
error severity, in addition to inband message. When a detected error severity triggers error pin
assertion, the corresponding error pin is asserted. Software must clear the error pin assertion by
clearing the global error status. The error pins can also be configured as general purpose outputs. In
this configuration, software can write directly to the error pin register to cause the assertion and
deassertion of the error pin.
The error pins are asynchronous signals.
11.3.2.2.6 PCIe INTx and MSI
PCIe INTx and MSI are supported through the PCIe standard error reporting. The IIO forwards the
MSI and INTx generated downstream to the Coherency Interface. The IIO PCIe ports themselves
generate MSI interrupt for error reporting if enabled. See the PCIe specification for more details on
the PCIe standard and advance error capability.