Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
38 Order Number: 323103-001
Notes:
1. System Memory timing support is based on availability and is subject to change.
2.1.3.1 System Memory Operating Modes
The IMC contains three DDR3 channel controllers. Up to three channels can be
operated independently or two channels (only channels A and B) can be paired for
lockstep or mirroring. The DRAM controllers share a common address decode and DMA
engines for RAS features. Configuration registers may be per channel or common. Each
DRAM controller has a scheduler, write and read data paths, ECC logic and auxiliary
structures.
Resilvering is not supported. A single block of logic is used to support Scrubbing and
Sparing, therefore these functions cannot be carried out simultaneously. To spare a
16 GB channel may take up to 40 seconds. The memory must be initialized to a valid
ECC before either patrol scrubbing or demand scrubbing can be enabled. The patrol
scrub rate is programmable. If the patrol scrub rate was programmed to one line every
82 ms, 64 GB would require one day to fully scrub once.
All IMC errors are categorized as either Corrected, Uncorrected Non-Fatal error (e.g.
Patrol scrub read), or Fatal. The IMC can be programmed to treat Uncorrected Non-
Fatal errors as Fatal. Corrected errors, including uncorrected errors on a mirrored
channel that are “corrected” by switching to a working partner, will not assert any
signal. These errors must be monitored by SW.
Any IMC uncorrected errors will be fatal. An asynchronous Machine Check exception is
signaled and the error is logged. The IMC can be configured to send a poison indication
with any uncorrectable error, this can be used to achieve system level error
containment.
Read and Write addresses are steered according to address decode to one of the three
channels or a pair of channels (in the mirroring or lockstep cases). The channels
decompose the reads and writes into precharge, activate, and column commands and
issue these commands on the DDR interface as command and address lines. Write data
is enqueued in the IMC write data buffers where partial writes are merged to form full
line writes. Read returns from the three channels are corrected if necessary, then
multiplexed back to the IMC read data buffer.
The memory channels are treated as logical channels. That is, write requests credits to
the IMC are maintained on a logical channel basis. The memory controller may
translate the channel select sent to one or two physical channels. The register that
controls the mapping of logical channels to physical channels is described in the
register section (see Volume 2 of the Datasheet). In addition, the conditions under
which software or hardware can modify this mapping is also described. Table 10
summarizes how the logical to physical channel mappings are made.
Table 9. DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
CMD Mode Notes
800 5 5 5 5 1n and 2n 1
800 6 6 6 5 1n and 2n 1
1066
777
61n and 2n 1
888
1333 8 8 8 7 2n 1
1333 9 9 9 7 2n 1