Datasheet
Reliability, Availability, Serviceability (RAS)
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
378 Order Number: 323103-001
— System interface is compromised.
— Inband reporting may be possible.
e.g. Uncorrectable tag error in cache, or Permanent PCIe link failure.
— Requires immediate logging and reporting of the error to CPU or legacy IIO.
11.3.2 Inband Error Reporting
Inband error reporting signals the system of a detected error via inband cycles. There are two
complementary inband mechanisms in the IIO. The first mechanism is synchronous reporting along
with transaction responses/completion. The second mechanism is asynchronous reporting of inband
error message or interrupt. These mechanisms are summarized as follows:
Synchronous inband error reporting:
• Reported through the transaction. Data Poison bit indication.
— Generally for uncorrectable data errors (e.g. uncorrectable data ECC error).
• Response status field in response header.
— Generally for uncorrectable error related to a transaction (e.g. failed response due to an error
condition).
• No Response
— Generally for uncorrectable error that has corrupted the requester information and returning
a response to the requester become unreliable. The IIO silently drops the transaction. The
requester will eventually time out and report an error.
Asynchronous inband error reporting:
• Reported through inband error or interrupt messages. A detected error triggers an inband
message to the legacy IIO or CPU.
• Errors are mapped to three error severities.
• Each severity can generates one of the following inband message.
—CPEI
—NMI
—SMI
—None
• Each error severity can also cause Error pin (ERR[2:0]) assertion in addition to the above inband
message.
• Fatal severity can cause viral in addition to the above inband message and error pin assertion.
Note: The Intel
®
Xeon
®
processor C5500/C3500 series does not support viral alert
generation.
• IIO PCIe root ports can generate MSI, or forward MSI/INTx from downstream devices as per the
PCIe specification.
11.3.2.1 Synchronous Inband Error Reporting
Synchronous error reporting is generally received by a component, where the receiver attempts to
take corrective action without notifying the system. If the attempt fails, or if corrective action is not
possible, synchronous error reporting may eventually trigger a system event via the asynchronous
reporting. Synchronous reporting includes the following.