Datasheet

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Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
374 Order Number: 323103-001
(from Intel
®
QPI, DMI, or PCI-Express) may hang interfaces that are not cleared by
a warm reset.
System activity is initiated by a request from a processor link. No I/O devices will
initiate requests until configured by a processor to do so.
The requirements for DDR_DRAMPWROK assertion are:
Signal must be monotonic.
100 ns minimum delay between VDDQ @ 1.425 V to DDR_DRAMPWROK @
Vihminspec (0.627 V).
DDR_DRAMPWROK must be asserted no later than VCCPWRGOOD assertion.
No relationship between DDR_DRAMPWROK and VccP ramp.
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