Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 373
Reset
10.4 Reset Timing Diagrams
For clarification, the different voltages used in the system are:
• VCC = Ungated power to core.
• VTT = Ungated power to uncore, IIO.
• VDD = Dram power.
See the following figure.
10.4.1 Cold Reset, CPU-Only Reset Timing Sequences
The PCH asynchronously deasserts PLTRST#. On the Intel
®
Xeon
®
processor C5500/
C3500 series, this PLTRST# deassertion is synchronized by the legacy processor and
sent to the non-legacy processor using the DP_SYNCRST# pin.
When the BIOS writes the IIO.SYRE.CPURESET bit (in legacy Intel
®
Xeon
®
processor
C5500/C3500 series) and triggers a CPU only Reset, the legacy IIO will ensure that its
own internal RESETO_N and the RESETO_N on the non-legacy processor are
deasserted deterministically.
10.4.2 Miscellaneous Requirements and Limitations
• Power rails and stable QPICLK and PECLK master clocks remain within
specifications through all but power-up reset.
• Frequencies described in this chapter are nominal.
• Warm reset can be initiated by code running on a processor, SMBus, or PCI agents.
• Warm reset is not guaranteed to correct all illegal configurations or malfunctions.
Software can configure sticky bits in the IIO to disable interfaces that will not be
accessible after a warm reset. Signaling errors or protocol violations prior to reset
Figure 72. Intel
®
Xeon
®
Processor C5500/C3500 Series System Diagram
VR 11.0 Glue
VCC/VCC3/12V
Pwr Sply
PS_ON_N
PWRGD_PS
VTT_PWRGD
VR11.1
Enable
VR_READY
VR Sys Mem Glue
DDR_
DRAMPWROK
5VDUAL
5Vstby
+12V
VCC
V_SM
1.5V
PWRGD_PS hold-off
On: 100-500ms
Off: 1ms
On: refer BL-C VR
1-13ms from
Enable to
VID_Read
250us-2.5ms
from VID_Read
to VCCP_set
1ms - 10ms
delay
5Vstby
10k
isolation
Glue
PCH
H_PWRGD
VR_READY_
3V
PWROK
SLP_S3b
CPU
PWRGD
Logic
PLTRST#
CPU_RESET#
SLP_S3#
Voltage
Translation
VDDPWRGD
Glue
~100ms delay
Optional ?
Voltage
Translation
PWRGD_3V
Voltage
Translation
VTT_PWRGD
VRMPWRGD
CPU
VTTPWRGD
VCCPWRGD
VDDPWRGD
Intel Xeon Processor C5500/
C3500 Series
IIO
RESETO_N
VCCPWRGD
VDDPWRGD
VTTPWRGD
RST_N
PLTRSTIN#
PWROK
(not connected)