Datasheet

Reset
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
372 Order Number: 323103-001
The Intel
®
Xeon
®
processor C5500/C3500 series will support either the legacy or the
non-legacy CPU being the boot processor. Selection of the boot processor is controlled
by the BIOS.
The Legacy IIO is always the firmware agent and either of the processors can fetch
code from the flash. The processors may then use a semaphore register in the IIO to
determine which processor is designated as the boot processor.
10.3 CPU-Only Reset
The BIOS typically requires a CPU-only reset for several functions, such as configuring
the CPU speed. This CPU-only reset occurs after the platform cold reset. If all CPUs
(one socket and two socket configurations) in the system are connected directly to the
IIO, then the flow for the CPU-only reset is straightforward and as described below.
To set the core frequency correctly, each socket BSP writes the range of supported
frequencies in an IIO scratch pad register (PLATFORM_INFO MSR). Each node BSP
reads the values written by the other node and computes the common frequency. Since
both BSPs use the same algorithm, both arrive at the same least common frequency
feasible. Each node BSP then updates its own FLEX_RATIO_MSR. Other conditions that
require CPU-only reset are handled in a similar fashion and the appropriate MSRs are
set at this point. A CPU-only reset is required for all of the new setting to take effect.
The legacy BSP sets the IIO.SYRE.CPURESET bit to force a CPU warm reset. In
response to setting the IIO.SYRE.CPURESET bit, the IIO asserts the internal CPU Reset
(RESETO_N) signal to warm reset the CPU only. Since each socket has its own IIO with
its own internal reset (RESETO_N) signal, the IIO drives the internal reset signal to the
socket to force the CPU-only reset deterministically.
In a dual-socket Intel
®
Xeon
®
processor C5500/C3500 series, when the system BSP is
ready for a CPU-only reset it follows the sequence:
1. Sets the IIO.SYRE.NL_SYNC_RESET_CPU_ONLY bit in the non-legacy IIO
2. Then sets the IIO.SYRE.CPURESET bit in the legacy IIO.
When the IIO.SYRE.CPURESET bit is set in the legacy IIO, the legacy IIO must ensure
that its own RESETO_N and the RESETO_N on the non-legacy Intel
®
Xeon
®
processor
C5500/C3500 series are asserted deterministically. To achieve this, the Legacy IIO
drives DP_SYNCRST# to the non-legacy IIO. This is the same pin used during initial
cold reset.
The non-legacy IIO samples DP_SYNCRST# asserted and distinguishes between a CPU-
only reset and all other reset conditions (power-on, powergood etc) by using the
IIO.SYRE.NL_SYNC_RESET_CPU_ONLY bit.
If IIO.SYRE.NL_SYNC_RESET_CPU_ONLY bit is clear, then the DP_SYNCRST#
assertion is a cold reset or a warm reset, the non-legacy IIO gets reset and then
RESETO_N is asserted to the non-legacy CPU
If IIO.SYRE.NL_SYNC_RESET_CPU_ONLY bit is set, then the DP_SYNCRST#
assertion is for a CPU-only warm reset. The non-legacy IIO is not reset. The non-
legacy IIO drives the RESETO_N to the non-legacy core complex.
This flow ensures that the RESETO_N to the legacy CPU is asserted at a known fixed
offset w.r.t. the cycle on which RESETO_N is asserted to the non-legacy CPU. The 96-
cycle RESET de-assertion heartbeat ensures determinism.