Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 37
Interfaces
Table 8. UDIMM Only Support
2.1.3 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every two clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
Table 7. Intel
®
Xeon
®
Processor C5500/C3500 Series with RDIMM Only Support
DIMM Slots
per Channel
DIMMs
Populated
per Channel
DIMM Type POR Speeds
Ranks per
DIMM (any
combination)
Population Rules
2 1 Registered DDR3 ECC 800, 1066, 1333 SR, DR Any combination of x4 and
x8 RDIMMs, with 1 Gb,
2 Gb, or 4 Gb DRAM density.
Populate DIMMs starting
with slot 0, furthest from
the CPU.
2 1 Registered DDR3 ECC 800, 1066 QR
2 2 Registered DDR3 ECC 800, 1066 SR, DR
2 2 Registered DDR3 ECC 800 SR, DR, QR
3 1 Registered DDR3 ECC 800, 1066, 1333 SR, DR
Any combination of x4 and
x8 RDIMMs, with 1 Gb, 2
Gb, or 4 Gb DRAM density.
Populate DIMMs starting
with slot 0, furthest from
the CPU.
3 1 Registered DDR3 ECC 800, 1066 QR
3 2 Registered DDR3 ECC 800, 1066 SR, DR
3 2 Registered DDR3 ECC 800 SR, DR, QR
3 3 Registered DDR3 ECC 800 SR, DR
DIMM
Slots per
Channel
DIMMs
Populated
per Channel
DIMM Type POR Speeds
Ranks per
DIMM (any
combination)
Population Rules
21
Unbuffered DDR3
(w/ or w/o ECC)
800, 1066, 1333 SR, DR
Any combination of x8 and x16
UDIMMs, with 1 Gb, 2 Gb, or
4 Gb DRAM density.
Populate DIMMs starting with
slot 0, furthest from the CPU.
22
Unbuffered DDR3
(w/ or w/o ECC)
800, 1066 SR, DR
31
Unbuffered DDR3
(w/ or w/o ECC)
800, 1066, 1333 SR, DR
32
Unbuffered DDR3
(w/ or w/o ECC)
800, 1066 SR, DR