Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
368 Order Number: 323103-001
8.7 Intel
®
QPI Power Management
L0 – Full performance, full power.
L1 – Turn off the link, longer latency back to L0.
Note: There is no L0s support in the internal Intel
®
QPI link.
8.8 Intel
®
QuickData Technology Power Management
The Intel
®
Xeon
®
processor C5500/C3500 series implements with Intel
®
QuickData
Technology support different device power states. The Intel
®
QuickData Technology
device supports the D0 device power state that corresponds to the fully-on state and a
pseudo D3 hot state. Intermediate device power states D1 and D2 are not supported.
Since there can be multiple permutations with Intel
®
QuickData Technology and/or its
client I/O devices supporting the same or different device power states, care must be
taken to ensure that power management capable operating system does not put the
Intel
®
QuickData Technology device into a lower device power (e.g. D3) state while its
client I/O device is fully powered on (i.e. D0 state) and actively using Intel
®
QuickData
Technology . Depending on how Intel
®
QuickData Technology is used under an OS
environment, this imposes different requirements on the device and platform
implementation.
8.8.1 Power Management w/Assistance from OS-Level Software
In this model, there is a Intel
®
QuickData Technology device driver, and the host OS
can power-manage the Intel
®
QuickData Technology device through this driver. The
software implementation must make sure that the appropriate power management
dependencies between the Intel
®
QuickData Technology device and its client I/O
devices are captured and reported to the operating system. This is to ensure that the
operating system does not send the Intel
®
QuickData Technology device to a low power
(e.g. D3) state while any of its client I/O devices are fully powered on (D0) and actively
using Intel
®
QuickData Technology . E.g., the operating system might attempt to
transition the device to D3 while placing the system into the S4 (hibernate) system
power state. In that process, it must not transition the Intel
®
QuickData Technology
device to D3 before transitioning all its client I/O devices to D3. In the same way, when
the system resumes to S0 from S4, the operating system must transition the Intel
®
QuickData Technology device from D3 to D0 before transitioning its client I/O devices
from D3 to D0.
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