Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 367
Power Management
8.5 PCIe Power Management
The IIO module supports the following link/device states and events:
• L0s as receiver and transmitter.
• L1 link state.
•ASPM L1 link state.
• L3 link state.
• MSI or GPE event on power manage events internally generated (on a PCI Express
port hotplug event) or received from PCI Express.
• D0 and D3 hot states on a PCI Express port.
• Wake from D3-hot on a hot plug event at a PCI Express port.
The IIO module does not support the following link states or events:
• No support L1a.
• No support L2 (i.e. no aux power to IIO module).
• No support for the in-band beacon on PCI Express link.
8.5.1 Power Management Messages
When the Intel
®
Xeon
®
processor C5500/C3500 series receives PM_PME messages on
its PCI Express port, including any internally generated PM_PME messages on a hotplug
event at a root port, it either propagates it to the PCH over the DMI link as an Assert/
De-assert_PMEGPE message or generates an MSI interrupt or generates Assert/De-
assert_Intx message. See the PCI Express Base Specification, Revision 1.1 for details
of when a root port internally generates PM_PME message on a hotplug event. When
the ‘Enable ACPI mode for PM’ Miscellaneous Control and Status Register
(MISCCTRLSTS) bit is set, GPE messages are used for conveying PM events on PCI
Express, otherwise MSI or INTx is generated.
The rules for GPE messages are similar to the standard PCI Express rules for
Assert_INTx and De-assert_INTx:
• Conceptually, the Assert_PMEGPE and De-assert_PMEGPE message pair constitutes
a "virtual wire" conveying the logical state of a PME signal.
• When the logical state of the PME virtual wire changes on a PCI Express port, the
IIO communicates this change to the PCH using the appropriate Assert_PMEGPE or
de-assert_PMEGPE messages.
Note: Duplicate Assert_PMEGPE and De-assert_PMEGPE messages have no affect, but are not
errors.
• The IIO tracks the state of the virtual wire on each port independently and presents
a "collapsed" version (Wire-OR’ed) of the virtual wires to the PCH.
See the IIO interrupts section for details of how these messages are routed to the
legacy PCH.
8.6 DMI Power Management
• Active power management support using L0/L0s/L1a state.
• All inputs and outputs disabled in L3 Ready state.
See Section 8.1.10, “Supported DMI Power States” for details.