Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
366 Order Number: 323103-001
entered an S-state. It must be cleared by SW. If SW were to leave this bit
asserted, then the CPU will attempt to go to Sx by writing the Sleep Enable bit,
do the RET, read the Wake Status bit as '1' and continue through the code
before the PMReq(S1) had been delivered. When the PMReq(S1) is delivered
the CPU will be executing some code and get halted in the middle.
e. There will never be a C-state and S-state transition simultaneously. The OS code
must never attempt to do a C-state transition after writing the Sleep Enable bit
in the PCH. C states are only allowed in S0. Likewise S state requests must not
be followed by MWAIT.
f. The BIOS writes the Sleep Type and Sleep Enable bits in the PCH, using IO write
cycles. After this, last remaining thread (Monarch Thread) halts itself.
2. The PCH sends Go_S1_Final on DMI since S1 is final state desired by PCH.
3. On receiving Go_S1_Final, IIO multicasts PMReq(S1) over Intel
®
QPI to CPUs
(for DP systems).
4. CPUs respond by CmpD(S1) and acknowledges the receipt. Since Interrupts have
already been disabled, no interrupts will be received by CPU though normal read/
write to memory may be received by uncore in S1 state.
a. All cores are halted.
b. After sending CmpD(S1), uncore may try to bring Intel
®
QPI link to L1 if no
activity is detected and queues are idle.
5. IIO module responds to CmpD(S1) from CPU by sending Ack_Sx to PCH over
DMI.
6. IIO and PCH may transition the DMI link to L0s autonomously from this sequence
when their respective active state L0s entry timers expire.
8.4.4 S1 -> S0 Transition
1. The PCH will get a wake event, such as interrupt, PBE (Pending Break Event), etc.
that causes it to force the system back to S0. For the S1 to S0 return, there is
handshake with internal agents so they know the system is in S0 again.
a. PCH does all internal hand shakes before it sends Go_S0 up the DMI.
2. The PCH generates Go_S0 VDM.
3. In response to its reception of Go_S0, IIO module multicasts a PMReq(S0)
message to all CPUs. Intel
®
QPI links may need to be brought back to L0 before the
message/s can be sent.
4. After receiving the response from all CPUs (CmpD(S0)), the IIO module sends
Ack_Sx Vendor Defined Message to PCH.
Note: The CPU has two modes of S1 states (low-power and high-power S1). In the low-power
S1, the CPU shuts off its core PLLs when the Intel
®
QPI link transitions to L1 due to
inactivity. Hence, it cannot respond to any other message such as VLW, including
interrupts from the low power S1 mode. To wake up the platform to S0, the CPU must
see a Go_S0 message issued first by the PCH before anything else.
8.4.5 S0 -> S3/S4/S5 Transition
The universe comprehended by the DMI specification consists of a single IIO and a
single PCH. It does not comprehend multiple IIO modules and PCHs.
In the S3 sleep state, the system context is maintained in memory. The IIO module,
DMI link and all standard PCI Express links will transition to L3 Ready before power is
removed, which then places the link in L3.