Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 365
Power Management
8.4 Device and Slot Power Limits
All add-in devices must power-on to a state in which they limit their total power
dissipation to a default maximum according to their form-factor (10 W for add-in edge-
connected cards). When the BIOS updates the slot power limit register of the root ports
within the IIO module, the IIO module will automatically transmit a
Set_Slot_Power_Limit message with corresponding information to the attached device.
It is the responsibility of the platform BIOS to properly configure the slot power limit
registers in the IIO module and failure to do so may result in attached end-points
remaining completely disabled to comply with the default power limitations associated
with their form-factors.
8.4.1 DMI Power Management Rules for the IIO Module
1. The IIO module must send the ACK-Sx for the Go_S0, G0_S1_temp(final),
GO_S1_RW, G0_S3/4/5 messages.
2. The IIO module is never permitted to send an ACK-Sx unless it has received one of
the above Go-S* messages.
3. The IIO module is permitted to send the RESET-WARN-ACK message at any time
after receiving the RESET-WARN message.
8.4.2 Support for P-States
The platform does not coordinate P-state transitions between CPU sockets with
hardware messages. As such, the IIO module supports, but is uninvolved with, P-state
transitions.
8.4.3 S0 -> S1 Transition
1. The OSPM performs the following functions:
a. To enter an S state the OS will send a message to all drivers that a sleep event
is occurring.
b. When the drivers have finished handling their devices and completed all
outstanding transactions, they each respond back to the OS.
c. OSPM after this will:
Disable Interrupts (except SMI which is invisible to OS)
Set TPR (Task Priority Register) high.
Write the fake SLP_EN, which triggers BIOS (SMI Handler).
Set up ACPI registers in the PCH.
d. Since the sleep routine in the OS was a call, the OSPM returns to the calling code
and waits in a loop polling on the wake status (WAK_STS) bit (until S0 state is
resumed). The Wake Status bit (PCH) can only be set by PCH after the PCH has
Table 125. ADR Self-Refresh Entry Timing - AC Characteristics (CMOS 1.5 V)
Symbol Parameter Min. Typ. Max. Unit Figure Notes
T
RFSH
Time required to sample DDR_ADR input as active 8 Clock Figure 71 1
T
DSR
Time required to complete DIMM self-refresh activation from
DDR_ADR input assertion (last CKE falling)
20 µs Figure 71 2
Notes:
1. Input is synchronized internally; no setup and hold times are required relative to clocks.
2. Assumes closed loop throttling mode and thermal conditions such that the DDR3 interface is not in a throttling mode.