Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
364 Order Number: 323103-001
— The BIOS initializes the memory controller. Just before enabling CKE the BIOS
redefines (pre-selected by the platform implementation) one of the Intel
®
3420
chipset GPIO pins as an output and drives it active. The BIOS also writes the
H[2:0]_REFRESH_THROTTLE_SUPPORT registers to arm the DDR_ADR pin to
trigger the ADR entry sequence. (The arming BIOS writes must be timed such
that the DDR3 is fully active - ~200 clocks after CKE rising.) If an ADR event
occurs after this point, it will result in an ADR trigger and ADR re-entry. Normal
recovery proceeds with the BIOS restoring the memory controller settings from
NVRAM The DDR3 is not initialized/scrubbed because it contains the preserved
ADR data.
8.3.2.5.4 Non-Volatile Save/Restore of MCU Configuration
The first time a system boots (no valid data assumed in DIMM), the BIOS is expected to
initialize and scrub memory. There is not sufficient time for software to save the
memory controller (MCU) register contents during a triggered ADR entry into self-
refresh sequence. Therefore, just like for S3, the MCU register settings must be stored
to non-volatile memory (flash or battery backed NVRAM) on first boot. Upon exit from
self-refresh, (just like S3 resume) the BIOS must make sure that it does not re-
initialize or scrub memory but instead restores the memory controller contents and
begins using the DDR3 memory (with knowledge of the memory space that it can
overwrite and which space should be left untouched).
Since with ADR the system could have been asynchronously taken down, unlike normal
S3 recovery, the OS cannot assume that its data structures in memory are valid and
must boot from scratch. Further, the OS must be aware of which memory space was
preserved, ascertain the integrity of this space (via its software protected data
structure), and handle re-allocating the protected space to the application(s).
8.3.2.5.5 Target ADR Entry Time
After the DDR_ADR signal is asserted, the DDR3 self-refresh entry sequence is initiated
by the Intel
®
Xeon
®
processor C5500/C3500 series memory controller (MCU). The end
of this sequence is where the MCU drives the CKE pins low, thus causing the DDR3
DIMMs to enter self-refresh mode. The system must sustain in-spec power delivery to
the processor rails continuously during ADR entry/exit and during the entire time that
the platform is in ADR.
The Intel
®
Xeon
®
processor C5500/C3500 series ADR entry target is 20μS, assuming
the DDR3 is operating in closed loop throttling mode and is not throttling. Open or
closed loop throttling conditions will significantly increase ADR entry time.
Figure 71. DDR_ADR to Self-Refresh Entry
DDR_ADR
PWRGOOD
DIMM Self-
refresh Complete
(last CKE falling)
T
RFSH
T
DSR