Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 363
Power Management
8.3.2.5.2 Pin-Triggered Self-Refresh Entry
ADR provides an external pin, DDR_ADR, that places the DDR3 into self-refresh. The
critical data, now all in the DDR3, can be preserved as long as power is maintained to
the DIMMs in self-refresh.
The interface and sequence for placing DDR3 in self-refresh is part of the existing
JEDEC DDR3 specification. DDR3 self-refresh entry involves commands being issued
from the memory controller to the DDR3 ending in the CKE signals for each DIMM/
RANK being driven low.
Pin-triggered ADR entry is initiated by a platform that has detected an abnormal
condition requiring system reboot. (During this time, the platform sustains full power
delivery to the Intel
®
Xeon
®
processor C5500/C3500 series.) Upon completion of ADR
entry, the DDR3 is in self-refresh mode. The ADR trigger pin is disabled by default and
therefore must be configured/enabled by the BIOS.
The platform must not set the DDR_ADR signal to the Intel
®
Xeon
®
processor C5500/
C3500 series until the BIOS has configured the DDR3 memory. The BIOS needs to
provide an indication that the memory is not yet configured to the platform. The BIOS
may use one of the GPIO pins on the Intel
®
3420 chipset for this purpose. In this case,
the BIOS will program one of the GPIOs as an output. The BIOS will drive this GPIO
active after the DDR3 memory configuration has been completed. The platform will use
this GPIO to conditionalize the presentation of DDR_ADR to the processor, i.e.
DDR_ADR will only be activated to the processor after the DDR3 memory is configured.
The programming of this GPIO will be persistent after the initial power up. I.e. it will
only be reset to the default after a power-down.
8.3.2.5.3 Power-On, Entry, and Exit Sequence
Three sequences are presented below: first power on, ADR entry, and ADR exit.
• First Power-ON Sequence
— The BIOS initializes the memory controller. Right before enabling CKE, the
BIOS redefines one of the Intel
®
3420 chipset GPIO pins (pre-selected by the
platform implementation) as an output and drives it active. The BIOS then
scrubs all DRAM. The BIOS also writes the
H[2:0]_REFRESH_THROTTLE_SUPPORT registers to arm the DDR_ADR pin to
trigger the ADR entry sequence. (The arming BIOS writes must be timed such
that the DDR3 is fully active - ~200 clocks after CKE rising.)
— Once armed, an DDR_ADR event will put the DDR3 memory into self-refresh as
described in the following section.
• ADR Entry Platform Sequence
— The platform sets DDR_ADR to Intel
®
Xeon
®
processor C5500/C3500 series.
—Intel
®
Xeon
®
processor C5500/C3500 series issues the command sequence for
self-refresh entry to the DDR3 memory eventually ending in all CKEs=0.
— The DDR3 memory enters and stays in self-refresh mode until the ADR exit
sequence is performed.
— The BIOS re-programs the selected GPIO to input mode and sets its state to
the power-on default, i.e. inactive.
Warning: The Intel
®
Xeon
®
processor C5500/C3500 series will not respond to the DDR_ADR
signal unless the ADR trigger enable bit is set (see the
CHL_CR_REFRESH_THROTTLE_SUPPORT register description). The BIOS is expected to
enable ADR triggering only after the DDR is fully enabled (~200 clocks post CKE rising
per DDR3 spec).
•ADR Exit Sequence