Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
362 Order Number: 323103-001
The Intel
®
Xeon
®
processor C5500/C3500 series contains the following integrated ADR
feature elements:
• Level-sensitive pin, DDR_ADR, that triggers DDR3 self-refresh entry.
• BIOS re-initialization of the memory controller triggers exit from DDR3 self-refresh.
A complete and robust memory backup implementation involves many areas of the
platform, e.g. hardware, BIOS, firmware OS, application, etc. The ADR mechanism
described in this section does not provide such a solution by itself. Although the ADR
mechanism can be used to implement a battery backup memory, the usage as
described in this section is focused on allowing rapid DDR3 self-refresh entry/exit to
facilitate system recovery during re-boot by preserving critical portions of memory. It is
assumed for the purposed of this section, that full power delivery is available
uninterruptedly during the ADR sequence. Since internal caches, buffers, etc. are not
committed to memory, the platform needs to implement protected software data
structures as appropriate.
Warning: The simplified ADR application described in this chapter is different from the storage
application of ADR. In the application described in this section, only data that is
committed to DDR3 memory when ADR is invoked is preserved; there are no provisions
for preservation of processor state, in-flight data, etc. In contrast, the storage
application of the ADR provides for preservation of certain data that is not in DDR3
memory when ADR is invoked.
Additional restrictions are that ADR is not supported in S2/S3/S5 or C3/C6 ACPI states
nor under memory controller RAS modes of sparing, lockstep, mirroring, x8, or while
using unbuffered DIMMs. Continual (back-to-back) inbound reads or writes of the same
location are not permitted.
ADR entry is quick (~20μS under non-throttling DDR3 conditions). In comparison, S3
entry takes significantly more time to drain the I/O and flush processor caches before
putting the memory into self-refresh. ADR is primarily targeted for systems and
thermal conditions in which the DDR3 does not throttle (assume closed-loop DDR3
monitor/control) because ADR entry time can increase significantly under DDR3
throttling conditions.
This document covers the ADR features integrated into the Intel
®
Xeon
®
processor
C5500/C3500 series and provides an overview of key platform and system software
requirements for a ADR solution.
8.3.2.5.1 Intel
®
Xeon
®
Processor C5500/C3500 Series ADR Use Model
The usage model is to allow preservation of memory contents with a fairly rapid entry/
exit latency. Data preservation of DDR3 memory is accomplished by placing the DDR3
memory into self-refresh. Only data that is committed to the memory when ADR is
invoked will be preserved. Other data, e.g. in flight data, interval processor context,
etc. will be lost. It is the platform software’s responsibility to implement appropriate
data structures to ensure that the DDR3 data of interest is correctly preserved prior to
using this data after ADR exit.
The key benefits of this usage model are rapid self-refresh entry/exit with low
overhead. A typical application for the ADR feature usage is the preservation of a large,
complex data structure that requires a relatively long time to create and may persist
across re-boots. An example of such a data structure is a routing table. For the
purposes of this usage model, it is assumed that full power delivery is sustained to the
Intel
®
Xeon
®
processor C5500/C3500 series during the entire ADR envelope.
Warning: In DP platforms, both processors must be placed into ADR at approximately the same
time.