Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 361
Power Management
The target behavior is to enter self-refresh for C3 and above states as long as there are
no memory requests to service. The target usage is shown in Table 124.
8.3.2.3 Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices into a power-down state.
The processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a larger
performance impact since all pages will be closed before putting the devices in power-
down mode.
If dynamic power-down is enabled, then all ranks are powered up before doing a
refresh cycle and all ranks are powered down at the end of refresh.
8.3.2.4 DRAM I/O Power Management
Unused signals shall be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM
control signals such as CS#, CKE, and ODT for unpopulated DIMM slots.
The I/O buffer for an unused signal shall be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals shall be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
8.3.2.5 Asynch DRAM Self Refresh (ADR)
The Asynchronous DRAM Refresh (ADR) feature in the Intel
®
Xeon
®
processor C5500/
C3500 series may be used to provide a mechanism to enable preservation of key data
in DDR3 system memory. ADR uses an input pin to the processor, DDR_ADR, to trigger
ADR entry. ADR entry places the DIMMs in self-refresh. Any data that is not committed
to memory when ADR activates is lost, i.e. in-flight data to/from memory, caches, etc.
are not preserved. In DP platforms, both processors need to be placed into ADR at
approximately the same time to prevent spurious memory requests. Otherwise, a
processor that is not in ADR may generate memory requests to the other processor’s
memory (in ADR).
Table 124. Targeted Memory State Conditions
Mode Memory State
C0, C1E Dynamic memory rank power down based on idle conditions.
C3, C6
Dynamic memory rank power down based on idle conditions
If there are no memory requests, then enter self-refresh. Otherwise use dynamic memory rank
power down based on idle conditions.
S1
S1 HP (high power - Intel
®
QPI in L1 is not supported): Dynamic memory rank power down
based on idle conditions.
S1 LP (low power - Intel
®
QPI in L1 supported): Dynamic memory rank power down based on
idle conditions. If there are no memory requests, then enter self-refresh. Otherwise use
dynamic memory rank power down based on idle conditions.
S3 Self Refresh Mode
S4 Memory power down (contents lost)
S5 Memory power down (contents lost)