Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
360 Order Number: 323103-001
8.2.5.4 Package C6 State
A processor enters the package C6 low power state when:
All cores are in C6 and the processor has been granted permission by the platform.
In the package C6 state, all cores save their architectural state and have their core
voltages reduced. The LLC is still powered and snoopable in this state. The processor
remains in package C6 state as long as any part of the LLC is still active.
8.3 IMC Power Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
8.3.1 Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices, (such as an unpopulated or
single-sided DIMM connector) is tri-stated. The benefits of disabling unused SM signals
are:
Reduced power consumption.
Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, as determined by the DRAM Rank Boundary
register values, then the corresponding chip select and SCKE signals are not driven.
SCKE tri-state should be enabled by the BIOS where appropriate, since at reset all rows
must be assumed to be populated.
8.3.2 DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives CKE pins to
perform these operations.
8.3.2.1 Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM whose level is recognized, other
than the DDR3 reset pin, once power is applied. It must be driven LOW by the DDR
controller to make sure the SDRAM components float DQ and DQS during power-up.
CKE signals remain LOW while any reset is active, until the BIOS writes to a
configuration register. With this method, CKE is guaranteed to remain inactive for
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
8.3.2.2 Conditional Self-Refresh
Intel
®
Rapid Memory Power Management (Intel
®
RMPM), which conditionally places
memory into self-refresh in the C3 and above states, is based on the state of the PCI
Express links.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then enters all SDRAM ranks into self-refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.