Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
36 Order Number: 323103-001
Notes:
2. x16 DRAM is not supported on combo routing.
3. Channel C can be used as a spare for channels on the same socket.
4. Between Channel A and B of the same socket. No resilvering to recover mirrored state after failure.
2.1.2 System Memory DIMM Configuration Support
• Table 7 summarizes the supported DIMM configurations for platforms that are
designed with RDIMM only support.
• Table 8 summarizes the supported DIMM configurations for platforms that are
designed with UDIMM only support.
Data Lines per DRAM x8, x16 x4, x8
Data Mask No
Lockstep Channel Support No
Yes, Channels A and B
Not supported with mirroring
or sparing
Error Correction Code Capability
Correction for any error within a x4 DRAM and all
connected data/strobe lines
Correction for any error within
a x8 DRAM and all connected
data/strobe lines
Each Cacheline Comes From One Channel Lockstepped Pair
Address Fault Detection None Address parity Address parity + ECC
Latency
Baseline, critical word first
optimizations
+3 UCLK, + .5 DCLK +3 UCLK, + .5 DCLK
Page Policy Open with adaptive idle timer or Closed Page
Intel
®
QPI Priority Yes No No
Graphics No
DIMM Sparing
2,3
No
Yes, entire channel spared,
within a socket only
No
Hot Add of DIMMs No
Hot Replace DIMMs No
Channel Mirroring
4
No
Within a socket
Channel A and B only
No
Demand Scrub
2
If ECC is enabled Yes
Patrol Scrub
2
If ECC is enabled Yes
Active and Precharge Power Down Yes, no support for turning off DRAM DLLs in pre-charge power down
Auto Refresh Yes
Throttling
Virtual Temp sensor with per command energies for bandwidth throttling and Open Loop
throttling. Closed Loop throttling via DDR_THERM# pin.
Dynamic 2X Refresh
Via MC_CLOSED_LOOP register. See the MC_Closed_Loop Register in Section 4.15.7 in
Volume 2 of the Datasheet.
Memory Init Yes
Memory Test
When ECC DIMMs are
present
Yes
Poisoning Yes
Asynchronous Self Refresh No
Table 6. System Memory Feature Summary (Sheet 2 of 2)
Feature Unbuffered DDR3
Independent Registered
DDR3
Lockstepped Registered
DDR3