Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
358 Order Number: 323103-001
The processor exits a package C-state when a break event is detected. If DRAM was
allowed to go into self-refresh in package C3 or C6 state, it will be taken out of self-
refresh. Depending on the type of break event, the processor does the following:
If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
If the break event is not masked, then the target core enters the core C0 state
and the processor enters package C0.
If the break event is masked, then the processor attempts to re-enter its
previous package state.
If the break event was due to a memory access or snoop request...
But the platform did not request to keep the processor in a higher power
package C-state, then the package returns to its previous C-state.
And if the platform requests a higher power C-state, then the memory access
or snoop request is serviced and the package remains in the higher power C-
state.
Table 123 shows package C-state resolution for a dual-core processor. Figure 70
summarizes package C-state transitions.
Note:
1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.
Table 123. Coordination of Core Power States at the Package Level
Package C-State
Core 1
C0 C1E
1
C3 C6
Core 0
C0 C0 C0 C0 C0
C1E
1
C0 C1E
1
C1E
1
C1E
1
C3 C0 C1E
1
C3 C3
C6 C0 C1E
1
C3 C6