Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 357
Power Management
While a core is in C1E state, it processes bus snoops and snoops from other threads.
For more information on C1E, see Section 8.2.5.2.
8.2.4.3 Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT (C3) instruction. A core in C3 state flushes the contents of its
instruction cache, data cache, and Mid-Level Cache (MLC) to the Last Level Cache
(LLC), while maintaining its architectural state. All core clocks are stopped at this point.
Because the core’s caches are flushed, the processor does not wake any core that is in
the C3 state when either a snoop is detected or when another core accesses cacheable
memory.
8.2.4.4 Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT (C6) instruction. Before entering Core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core can lower its voltage to any voltage,
even as low as zero volts. During exit, the core is powered on and its architectural state
is restored.
8.2.4.5 C-State Auto-Demotion
In general, deeper C-states, such as C6, have long latencies and higher energy entry/
exit costs. The resulting performance and energy penalties become significant when
the entry/exit frequency of a deeper C-state is high. Therefore incorrect or inefficient
usage of deeper C-states have a negative impact on power savings. In order to
increase residency and improve battery life in deeper C-states, the processor supports
C-state auto-demotion.There are two C-State auto-demotion options:
•C6 to C3
• C6/C3 To C1E
The decision to demote a core from C6 to C3 or C3/C6 to C1E is based on each core’s
immediate residency history. Upon each core C6 request, the core C-state is demoted
to C3 or C1E until a sufficient amount of residency has been established. At that point,
a core is allowed to go into C3/C6. Each option can be run concurrently or individually.
This feature is disabled by default. The BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
8.2.5 Package C-States
The processor supports C0, C1E, C3,and C6 power states. The following is a summary
of the general rules for package C-state entry. These apply to all package C-states
unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor. If given permission, the DRAM will be put into self-refresh in the
package C3 and C6.