Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
356 Order Number: 323103-001
Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and redirected to MWAIT instructions. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx)
request. They fall through like a normal I/O instruction.
Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF' feature which triggers a wakeup
on an interrupt even if interrupts are masked by EFLAGS.IF.
8.2.4 Core C-States
Changes in the Intel
®
Core
TM
i7 microarchitecture as well as changes in the platform
have altered the behavior of C-states as compared to prior Intel platform generations.
Signals such as STPCLK#, SLP#, and DPSLP# are no longer used, which eliminates the
need for C2 state. In addition, the latency of the C6 state within the new
microarchitecture is similar to that of C4 in the Intel Core microarchitecture. Therefore
the C4 state is no longer necessary. The following are general rules for all core C-
states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (e.g., thread0
requests C1E while thread1 requests C3, resulting in a core C1E state).
• A core transitions to C0 state when:
— An interrupt occurs.
— There is an access to the monitored address if the state was entered via an
MWAIT instruction.
• For core C1E, and core C3, an interrupt directed toward a single thread wakes only
that thread. However, since both threads are no longer at the same core C-state,
the core resolves to C0.
• For core C6, an interrupt coming into either thread wakes both threads into C0
state.
• Any interrupt coming into the processor package may wake any core.
Note: The core “C” state resolves to the highest power dissipation “C” state of the threads.
8.2.4.1 Core C0 State
The normal operating state of a core where code is being executed.
8.2.4.2 Core C1E State
C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either the normal
state or the C1E state. See the Intel
®
64 and IA-32 Architecture Software Developer’s
Manual, Volume 3A/3B: Stem Programmer’s Guide for more information.
Table 122. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes
P_LVL2 MWAIT(C3) The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR.
P_LVL3 MWAIT(C6) C6. No sub-states allowed